摘要：
该处理基于APB注册接口访问。默认情况下，寄存器PHY_ RSTZ激活PHY resetsphyshutdown z，物理测试并在默认情况下启用寄存器PHY_TEST_CTRL0，而不激活测试电路。所有PHY resets都将被激活。默认情况下，PHY RSTZ寄存器已重置PHYphyshutdownz、phyrstz并禁用enableclk，寄存器PHY_TEST_CTR0默认关闭testclr引脚。默认情况下，所有phyreset管脚都处于活动状态+---------------------------------------------+| MIPI_ DSI_ PHY_ RSTZfielddescriptions |+--------------------------------------------+| Field | Description |+------------------------------------------------+-------------------------------------------------+| 31–3 | |-|保留|+-----------------------------------------------+| 2 | | PHY_enableclk | EnablesD-PHYClockLaneModulewhen1|+----------------+--------------------------------------------------+|1|D-phy重置禁用（1），用于访问||phy重置状态的||phy_ rstz|数字部分|+-------------+----------------------------------------------+|0|D-PHYShutdowndisablewhen1，used topace | | phy_ shutdownz |完整的phy宏关闭|+----------------+--------------------------------------------------+配置寄存器phy_IF_ CFG，并纠正控制器使用的嵌套数。通过配置PHY_IF_CFG寄存器来配置控制器的通道数+---------------------------------------------------------------------+| MIPI_ DSI_ PHY_IF_ CFG_字段描述|+-------------------+-------------------------------------------------+|字段|描述|+---------------+-------------------------------------------------+|31–10 | | |-|保留|+-------------------+------------------------------------------------+|9–2 |配置请求的最短等待时间||phy_ stop_wait_|在||时间|时钟周期|+----------------+--------------------------------------------------+|1–0|活动数据链的数量。||n_lanes|001DataLane|||012DataLanes|||103DataLanes|| |114DataLanes|+-----------------+-------------------------------------------------+将TX_ ESCclock频率配置为低于20MHz的频率，即D-PHYSCAPE模式的最大允许频率。这是通过在寄存器CLKMGR_ CFG、字段TX_ ESC_ CLK_ DIVISION.TX _ ESC_ CL K_ DIVICIONdivides ByteClock中写入来实现的。配置TX_当ESC时钟频率低于20MHz时，使用D-PHYSCAPE模式_ CFG寄存器_ ESC_ CLK_DIVISION的TX。
MIPI DSI 和 D-PHY 初始化序列 2015-12-29 深圳 南山平山村 曾剑锋 参考文档： i.MX 6Dual/6Quad Multimedia Applications Processor Reference Manual 43.4 Programming 43.4.1 DSI and D-PHY initialization sequence 43.4.1 DSI 和 D-PHY 初始化序列 This chapter describes the procedure for DSI and D-PHY initialization. This process is based on APB register interface access. 这一章描述了DSI和D-PHY初始化的过程。处理过程是基于APB注册接口访问。 • By default register PHY_RSTZ is activating the PHY resets physhutdownz, phyrstz and disabling enableclk and register PHY_TEST_CTRL0 is by default asserting the testclr pin. All the PHY reset pins are being activated by default. 默认情况下PHY_RSTZ寄存器已经重置PHY physhutdownz,phyrstz和禁用enableclk，寄存器PHY_TEST_CTRL0是默认情况下关闭testclr引脚的。所有的phy resset引脚默认都是激活的。 +---------------------------------------------------------------+ | MIPI_DSI_PHY_RSTZ field descriptions | +---------------+-----------------------------------------------+ | Field | Description | +---------------+-----------------------------------------------+ | 31–3 | | | - | Reserved | +---------------+-----------------------------------------------+ | 2 | | | phy_enableclk | Enables D-PHY Clock Lane Module when 1 | +---------------+-----------------------------------------------+ | 1 | D-PHY Reset disable when 1, used to place the | | phy_rstz | digital section of D-PHY in reset state | +---------------+-----------------------------------------------+ | 0 | D-PHY Shutdown disable when 1, used to place | | phy_shutdownz | the complete D-PHY macro in power down | +---------------+-----------------------------------------------+ • Configure Register PHY_IF_CFG with correct the number of lanes to be used by the controller. 通过配置PHY_IF_CFG寄存器来配置控制器的lane的数量。 +-------------------------------------------------------------------+ | MIPI_DSI_PHY_IF_CFG_ field descriptions | +----------------+--------------------------------------------------+ | Field | Description | +----------------+--------------------------------------------------+ | 31–10 | | | - | Reserved | +----------------+--------------------------------------------------+ | 9–2 | Configures minimum wait period to request an HS | | phy_stop_wait_ | transmission after the stop state accounted in | | time | clock lane cycles | +----------------+--------------------------------------------------+ | 1–0 | Number of active data lanes. | | n_lanes | 00 1 Data Lane (Lane 0) | | | 01 2 Data Lanes (Lane 0, and 1) | | | 10 3 Data Lanes (Lane 0,1 and 2) | | | 11 4 Data Lanes (All) | +----------------+--------------------------------------------------+ • Configure the TX_ESC clock frequency to a frequency lower than 20MHz that is the maximum allowed frequency for D-PHY ESCAPE mode. This is done by writing in Register CLKMGR_CFG, field TX_ESC_CLK_DIVISION. TX_ESC_CLK_DIVISION divides Byte Clock and generates a TX_ESC clock for the D-PHY. (Note: Byte clock is limited to 125MHz (1GHz/8bits) and by writing TX_ESC_CLK_DIVISION=0x07 TX_ESC clock will always be lower than 20MHz) 配置TX_ESC时钟频率小于20MHz给D-PHY ESCAPE模式，通过向CLKMGR_CFG寄存器的TX_ESC_CLK_DIVISION进行配置。TX_ESC_CLK_DIVISION对Byte Clock进行分频，并对生成TX_ESC时钟给D-PHY。（注意：Byte clock被限制在125MHz（1GHz/8bit），并且对TX_ESC_CLK_DIVISION=0x07 TX_ESC 时钟将总是小于20MHz） +-------------------------------------------------------------------+ | MIPI_DSI_CLKMGR_CFG field descriptions | +-------------+-----------------------------------------------------+ | Field | Description | +-------------+-----------------------------------------------------+ | 31–16 | | | - | Reserved | +-------------+-----------------------------------------------------+ | 15–8 | Division factor for Time Out clock used as timing | | TO_CLK_ | unit in the configuration of HS to LP and LP to HS | | DIVIDSION | transition error. | +-------------+-----------------------------------------------------+ | 7–0 | Division factor for TX ESCAPE clock source ( | | TX_ESC_CLK_ | lanebyteclk pin), values 0 and 1 stop TX_ESC | | DIVIDSION | clock generation. | +-------------+-----------------------------------------------------+ • Configure the DPHY PLL clock frequency through the TEST Interface to operate at 1GHz, assuming that the REF_CLK is provided with a frequency of 27MHz 假设REF_CLk提供的27MHz频率，通过TEST接口操作配置DPHY PLL时钟频率达到1GHz。 +---------------------------------------------------------------------------+ | MIPI_DSI_PHY_TST_CTRL0 field descriptions | +-------------+-------------------------------------------------------------+ | Field | Description | +-------------+-------------------------------------------------------------+ | 31–2 | | | - | Reserved | +-------------+-------------------------------------------------------------+ | 1 | PHY test interface strobe signal. Used to clock TESTDIN bus | | phy_testclk | into the D-PHY. In conjunction with TESTEN signal controls | | | the operation selection | +-------------+-------------------------------------------------------------+ | 0 | PHY test interface clear. When active performs vendor | | phy_testclr | specific interface initialization (Active High) | +-------------+-------------------------------------------------------------+ +----------------------------------------------------------------------------------+ | MIPI_DSI_PHY_TST_CTRL1 field descriptions | +--------------+-------------------------------------------------------------------+ | Field | Description | +--------------+-------------------------------------------------------------------+ | 31–17 | | | - | Reserved | +--------------+-------------------------------------------------------------------+ | 16 | PHY test interface operation selector: when 1 configures address | | phy_testen | write operation on the falling edge of TESTCLK; when 0 configures | | | a data write operation on the rising edge of TESTCLK | +--------------+-------------------------------------------------------------------+ | 15–8 | PHY output 8-bit data bus for read-back and internal probing | | phy_testdout | functionalities | +--------------+-------------------------------------------------------------------+ | 7–0 | PHY test interface input 8-bit data bus for internal register | | phy_testdin | programming and test functionalities access | +--------------+-------------------------------------------------------------------+ • Write @ PHY_TST_CTRL0 - 32'h00000000 this disables the testclr pin enabling the interface to write new values to the DPHY internal registers. 往PHY_TST_CTRL0写入32'h00000000，禁用testclr引脚，同时使能接口往DPHY内部寄存器中写值 • Write @ PHY_TST_CTRL1 - 32'h00010044 this enables the testen pin bit 17 of this Core register and configures the testdatain to 8'h44. This operation initiate the configuration process of the test code number 0x44. 往PHY_TST_CTRL1写入32'h00010044，使能testen引脚核心寄存器17位，并配置testdatain值为8'h44，这个操作启动配置test code number 0x44。 • Write @ PHY_TEST_CTRL0 - 32'h0000002 followed by a new write to PHY_TEST_CTRL0 - 32'h00000000. This operation toggles the testclk (bit 2) and the testdin will be sampled on the falling edge of testclk latching a new test code. 往PHY_TST_CTRL0写入32'h00000002总是跟随在往PHY_TST_CTRL0写入32'h00000000之后，这个操作触发testclk（bit2），并将testddatain的数据采样生成一个新的test code • Write @ PHY_TEST_CTRL1 - 32'h00000074 disabling the testen pin and configuring testdatain to 8'h74. This operation prepares the interface to load in test code 0x44 the 0x74 value. • Write @ PHY_TEST_CTRL0 - 32'h00000002 followed by a new write to PHY_TEST_CTRL0 - 32'h00000000. This operation toggles the testclk and the testdin will be sampled on the rising edge of testclk latching a new content data to the configured test code. • Write @ PHY_RSTZ - 32'h00000007. This operation asserts physhutdownz, phyrstz and enableclk releasing the PHY from power down. The PHY will startup the PLL locking procedure to 1GHz operation. 往PHY_RSTZ写入32'h00000007这操作打断physhutdownz, phyrstz和使能时钟，让PHY从断电状态恢复，PHY将重启PLL锁到1GHz操作。 • Read @ PHY_STATUS - 32'hxxxxxxx1, until bit 0 phylock is detected at 1 signaling that PLL is locked and that a stable byte clock is being provided to the DSI host controller. 读取PHY_STATUS的值32'hxxxxxxx1，直到该寄存器的bit 0位被检查到1，说明PLL的锁住了，并且其在一个稳定的byte clock可以被提供到DSI主控制器 • Read @ PHY_STATUS - 32'hxxxxx1x1, until bit 2 phystopstateclklane is read '1' identifying that Clock Lane is in Stop State. Clock lane need to be in Stop state so that the D-PHY can switch to other operational states such as the High Speed mode. 读取PHY_STATUS的值32'hxxxxx1x1，直到该寄存器的bit 2位被检查到1，确定Clock lane在Stop状态。Clock lane需要进入Stop状态，这样D-PHY才能切换到其他的操作状态，如：High Speed mode。 • Write register PHY_IF_CTRL bit 0 to generate High Speed clock (txrequestHSclk). 往PHY_IF_CTRL中bit 0写入1，生成High Speed clock(txrequestHSclk)。 • Only after: 1) PLL locked and 2) Clock lane in Stop-State; the PHY will drive the correct LP sequence to configure the receiver end for HS. 只有在以下条件下继续运行： 1. PLL被锁住； 2. Clock lane进入Stop-State状态，PHY将驱动正确的LP序列去配置从设备，并进入HS状态。 • D-PHY starts transmitting HS clock on the Clock Lane. D-PHY 开始传送HS clock在Clock Lane上面。