spi协议--Verilog及仿真

modulespi(
inputsys_clk,
inputsys_rst_n,
inputi_tx_en,
inputi_rx_en,
input [7:0]i_data_in,
output reg[7:0]o_data_out,
output rego_tx_done,
output rego_rx_done,
//spi的四根信号线
inputMISO,
output regSCLK,
output regCS,
output regMOSI
);

reg [3:0]tx_state;
reg [3:0]rx_state;

always @(posedge sys_clk or negedge sys_rst_n)begin
if(!sys_rst_n)begintx_state<=4'd0;
rx_state<=4'd0;
o_data_out<=8'd0;
o_tx_done<=1'b0;
o_rx_done<=1'b0;
SCLK<=1'b0;
CS<=1'b0;
MOSI<=1'b0;
end
else if(i_tx_en)beginCS<=1'b0;//片选信号为0，表示开始发送
case(tx_state)
4'd1,4'd3,4'd5,4'd7,4'd9,4'd11,4'd13,4'd15:beginSCLK<=1'b1;
tx_state<=tx_state+1'b1;
o_tx_done<=1'b0;
end
4'd0:begin
SCLK<=1'b0;
MOSI<=i_data_in[7];
o_tx_done<=1'b0;
tx_state<=tx_state+1'b1;
end
4'd2:begin
SCLK<=1'b0;
MOSI<=i_data_in[6];
o_tx_done<=1'b0;
tx_state<=tx_state+1'b1;
end
4'd4:begin
SCLK<=1'b0;
MOSI<=i_data_in[5];
o_tx_done<=1'b0;
tx_state<=tx_state+1'b1;
end
4'd6:begin
SCLK<=1'b0;
MOSI<=i_data_in[4];
o_tx_done<=1'b0;
tx_state<=tx_state+1'b1;
end
4'd8:begin
SCLK<=1'b0;
MOSI<=i_data_in[3];
o_tx_done<=1'b0;
tx_state<=tx_state+1'b1;
end
4'd10:begin
SCLK<=1'b0;
MOSI<=i_data_in[2];
o_tx_done<=1'b0;
tx_state<=tx_state+1'b1;
end
4'd12:begin
SCLK<=1'b0;
MOSI<=i_data_in[1];
o_tx_done<=1'b0;
tx_state<=tx_state+1'b1;
end
4'd14:begin
SCLK<=1'b0;
MOSI<=i_data_in[0];
o_tx_done<=1'b1;
tx_state<=tx_state+1'b1;
end
default:tx_state<=4'd0;
endcase
end
else if(i_rx_en)beginCS<=1'b0;//片选信号为0，表示开始接收
case(rx_state)
4'd0,4'd2,4'd4,4'd6,4'd8,4'd10,4'd12,4'd14:beginSCLK<=1'b0;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b0;
end
4'd1:begin
SCLK<=1'b1;
o_data_out[7]<=MISO;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b0;
end
4'd3:begin
SCLK<=1'b1;
o_data_out[6]<=MISO;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b0;
end
4'd5:begin
SCLK<=1'b1;
o_data_out[5]<=MISO;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b0;
end
4'd7:begin
SCLK<=1'b1;
o_data_out[4]<=MISO;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b0;
end
4'd9:begin
SCLK<=1'b1;
o_data_out[3]<=MISO;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b0;
end
4'd11:begin
SCLK<=1'b1;
o_data_out[2]<=MISO;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b0;
end
4'd13:begin
SCLK<=1'b1;
o_data_out[1]<=MISO;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b0;
end
4'd15:begin
SCLK<=1'b1;
o_data_out[0]<=MISO;
rx_state<=rx_state+1'b1;
o_rx_done<=1'b1;
end
default:rx_state<=4'd0;
endcase
end
else begintx_state<=4'd0;
rx_state<=4'd0;
o_data_out<=8'd0;
o_tx_done<=1'b0;
o_rx_done<=1'b0;
SCLK<=1'b0;
CS<=1'b1;//片选信号为1，表示停止数据的接收
MOSI<=1'b0;
end
end
endmodule 

`timescale 1ns/1ns
modulespi_tb;
regsys_clk;
regsys_rst_n;
regi_tx_en;
regi_rx_en;
reg [7:0]i_data_in;
regMISO;
wire [7:0]o_data_out;
wireo_tx_done;
wireo_rx_done;
wireSCLK;
wireCS;
wireMOSI;
spi u_spi(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.i_tx_en (i_tx_en),
.i_rx_en (i_rx_en),
.i_data_in (i_data_in),
.o_data_out (o_data_out),
.o_tx_done (o_tx_done),
.o_rx_done (o_rx_done)
);
initial beginsys_clk=0;
sys_rst_n=0;
#10 sys_rst_n=1;
i_tx_en=1;
i_rx_en=0;
i_data_in=8'b0;
MISO=0;
end
always #10 sys_clk=~sys_clk;
always @(posedge sys_clk or negedge sys_rst_n)begin
if(!sys_rst_n)
i_data_in=8'b0000_0000;
else if(i_data_in==8'b1111_1111)begin
i_tx_en=0;
i_data_in=8'b0000_0000;
end
else if(o_tx_done)
i_data_in=i_data_in+1'b1;
end
endmodule