【高速接口-RapidIO】5、Xilinx RapidIO核例子工程源码分析

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48 `timescale 1ps/1ps
49 (* DowngradeIPIdentifiedWarnings = "yes" *)
50 
51 
52 modulesrio_example_top_srio_gen2_0 #(
53     parameter SIM_VERBOSE               = 1, //If set, generates unsynthesizable reporting
54     parameter VALIDATION_FEATURES       = 1, //If set, uses internal instruction sequences for hw and sim test
55     parameter QUICK_STARTUP             = 1, //If set, quick-launch configuration access is contained here
56     parameter STATISTICS_GATHERING      = 1, //If set, I/O can be rerouted to the maint port [0,1]
57     parameter C_LINK_WIDTH              = 1
58 )
59    //port declarations ----------------
60 (
61     //Clocks and Resets
62     input            sys_clkp,              //MMCM reference clock
63     input            sys_clkn,              //MMCM reference clock
64 
65     input            sys_rst,               //Global reset signal
66 
67     //high-speed IO
68     input           srio_rxn0,              //Serial Receive Data
69     input           srio_rxp0,              //Serial Receive Data
70 
71 
72 
73     output          srio_txn0,              //Serial Transmit Data
74     output          srio_txp0,              //Serial Transmit Data
75 
76 
77 
78     input           sim_train_en,           //Set this only when simulating to reduce the size of counters
79     output  [7:0]   led0
80 
81 );
82    //----------------------------------
83 
84 
85   //wire declarations ----------------
86 //
87 //-----------------------------------------------------------------------------
88 //Note : Below portion of the wire declaration should be commented when
89 //used in non-shared mode AND the SRIO core 2nd instance is used to share
90 //common logic like clk, rst and GT Common with another instance of SRIO
91 //with Shared Logic (in DUT) option if the simulator throws errors.
92 //-----------------------------------------------------------------------------
93     wirelog_clk;
94     wirephy_clk;
95     wiregt_pcs_clk;
96     wirelog_rst;
97     wirephy_rst;
98     wire            clk_lock;               //asserts from the MMCM
99 //
100 
101     //signals into the DUT
102 
103 
104     wireireq_tvalid;
105     wireireq_tready;
106     wireireq_tlast;
107     wire   [63:0]   ireq_tdata;
108     wire   [7:0]    ireq_tkeep;
109     wire   [31:0]   ireq_tuser;
110 
111     wireiresp_tvalid;
112     wireiresp_tready;
113     wireiresp_tlast;
114     wire    [63:0]  iresp_tdata;
115     wire    [7:0]   iresp_tkeep;
116     wire    [31:0]  iresp_tuser;
117 
118     wiretreq_tvalid;
119     wiretreq_tready;
120     wiretreq_tlast;
121     wire    [63:0]  treq_tdata;
122     wire    [7:0]   treq_tkeep;
123     wire    [31:0]  treq_tuser;
124 
125     wiretresp_tvalid;
126     wiretresp_tready;
127     wiretresp_tlast;
128     wire   [63:0]   tresp_tdata;
129     wire   [7:0]    tresp_tkeep;
130     wire   [31:0]   tresp_tuser;
131 
132     wire            maintr_rst = 1'b0;
133 
134     wiremaintr_awvalid;
135     wiremaintr_awready;
136     wire   [31:0]   maintr_awaddr;
137     wiremaintr_wvalid;
138     wiremaintr_wready;
139     wire   [31:0]   maintr_wdata;
140     wiremaintr_bvalid;
141     wiremaintr_bready;
142     wire   [1:0]    maintr_bresp;
143 
144     wiremaintr_arvalid;
145     wiremaintr_arready;
146     wire   [31:0]   maintr_araddr;
147     wiremaintr_rvalid;
148     wiremaintr_rready;
149     wire   [31:0]   maintr_rdata;
150     wire   [1:0]    maintr_rresp;
151 
152     //signals from Validation modules
153     wireval_ireq_tvalid;
154     wireval_ireq_tready;
155     wireval_ireq_tlast;
156     wire   [63:0]   val_ireq_tdata;
157     wire   [7:0]    val_ireq_tkeep;
158     wire   [31:0]   val_ireq_tuser;
159 
160     wireval_iresp_tvalid;
161     wireval_iresp_tready;
162     wireval_iresp_tlast;
163     wire    [63:0]  val_iresp_tdata;
164     wire    [7:0]   val_iresp_tkeep;
165     wire    [31:0]  val_iresp_tuser;
166 
167     wireval_treq_tvalid;
168     wireval_treq_tready;
169     wireval_treq_tlast;
170     wire    [63:0]  val_treq_tdata;
171     wire    [7:0]   val_treq_tkeep;
172     wire    [31:0]  val_treq_tuser;
173 
174     wireval_tresp_tvalid;
175     wireval_tresp_tready;
176     wireval_tresp_tlast;
177     wire   [63:0]   val_tresp_tdata;
178     wire   [7:0]    val_tresp_tkeep;
179     wire   [31:0]   val_tresp_tuser;
180 
181     wireval_maintr_awvalid;
182     wireval_maintr_awready;
183     wire   [31:0]   val_maintr_awaddr;
184     wireval_maintr_wvalid;
185     wireval_maintr_wready;
186     wire   [31:0]   val_maintr_wdata;
187     wireval_maintr_bvalid;
188     wireval_maintr_bready;
189     wire   [1:0]    val_maintr_bresp;
190 
191     wireval_maintr_arvalid;
192     wireval_maintr_arready;
193     wire   [31:0]   val_maintr_araddr;
194     wireval_maintr_rvalid;
195     wireval_maintr_rready;
196     wire   [31:0]   val_maintr_rdata;
197     wire   [1:0]    val_maintr_rresp;
198 
199 
200 //--
201 //----------------------------------------------------------------------------//
202 
203 
204 //--
205 
206     //other core output signals that may be used by the user
207     wire     [23:0] port_timeout;           //Timeout value user can use to detect a lost packet
208     wire            phy_rcvd_mce;           //MCE control symbol received
209     (* mark_debug = "true" *)
210     wire            phy_rcvd_link_reset;    //Received 4 consecutive reset symbols
211     wire            port_error;             //In Port Error State
212     //(* mark_debug = "true" *)//this constraint is commented as it is failing due to new MLO flow
213     wire            mode_1x;                //Link is trained down to 1x mode
214     wire            srio_host;              //Endpoint is the system host
215     wire    [223:0] phy_debug;              //Useful debug signals
216     
217     wire            gtrx_disperr_or;        //GT disparity error (reduce ORed)
218     
219     wire            gtrx_notintable_or;     //GT not in table error (reduce ORed)
220     wire     [15:0] deviceid;               //Device ID
221     wire            port_decode_error;      //No valid output port for the RX transaction
222     (* mark_debug = "true" *)
223     wire            idle_selected;          //The IDLE sequence has been selected
224     (* mark_debug = "true" *)
225     wire            idle2_selected;         //The PHY is operating in IDLE2 mode
226     wire            autocheck_error;        //when set, packet didn't match expected
227     (* mark_debug = "true" *)
228     wire            port_initialized;       //Port is Initialized
229     (* mark_debug = "true" *)
230     wire            link_initialized;       //Link is Initialized
231     wire            exercise_done;          //sets when the generator(s) has completed
232 
233     //other core output signals that may be used by the user
234     wire            phy_mce = 1'b0;         // Send MCE control symbol
235     wire            phy_link_reset = 1'b0;  // Send link reset control symbols
236     wire            force_reinit = 1'b0;    // Force reinitialization
237 
238 
239     //convert to ports when not using the pattern generator
240 
241 
242     wireaxis_ireq_tvalid;
243     wireaxis_ireq_tready;
244     wireaxis_ireq_tlast;
245     wire   [63:0]   axis_ireq_tdata;
246     wire   [7:0]    axis_ireq_tkeep;
247     wire   [31:0]   axis_ireq_tuser;
248 
249     wireaxis_iresp_tvalid;
250     wireaxis_iresp_tready;
251     wireaxis_iresp_tlast;
252     wire    [63:0]  axis_iresp_tdata;
253     wire    [7:0]   axis_iresp_tkeep;
254     wire    [31:0]  axis_iresp_tuser;
255 
256     wireaxis_treq_tvalid;
257     wireaxis_treq_tready;
258     wireaxis_treq_tlast;
259     wire    [63:0]  axis_treq_tdata;
260     wire    [7:0]   axis_treq_tkeep;
261     wire    [31:0]  axis_treq_tuser;
262 
263     wireaxis_tresp_tvalid;
264     wireaxis_tresp_tready;
265     wireaxis_tresp_tlast;
266     wire   [63:0]   axis_tresp_tdata;
267     wire   [7:0]    axis_tresp_tkeep;
268     wire   [31:0]   axis_tresp_tuser;
269 
270     wire            axis_maintr_rst = 1'b0;
271     wire            axis_maintr_awvalid = 1'b0;
272     wireaxis_maintr_awready;
273     wire   [31:0]   axis_maintr_awaddr = 1'b0;
274     wire            axis_maintr_wvalid = 1'b0;
275     wireaxis_maintr_wready;
276     wire   [31:0]   axis_maintr_wdata = 1'b0;
277     wire   [3:0]    axis_maintr_wstrb = 1'b0;
278     wireaxis_maintr_bvalid;
279     wire            axis_maintr_bready = 1'b0;
280     wire   [1:0]    axis_maintr_bresp;
281 
282     wire            axis_maintr_arvalid = 1'b0;
283     wireaxis_maintr_arready;
284     wire   [31:0]   axis_maintr_araddr = 1'b0;
285     wireaxis_maintr_rvalid;
286     wire            axis_maintr_rready = 1'b0;
287     wire   [31:0]   axis_maintr_rdata;
288     wire   [1:0]    axis_maintr_rresp;
289 
290     wireireq_autocheck_error;
291     wireireq_request_done;
292     wiremaint_autocheck_error;
293     wiremaint_done;
294 
295     //Vivado debug outputs for control of
296     (* mark_debug = "true" *)
297     wirepeek_poke_go;
298     (* mark_debug = "true" *)
299     wire [23:0]     user_addr;
300     (* mark_debug = "true" *)
301     wire  [3:0]     user_ftype;
302     (* mark_debug = "true" *)
303     wire  [3:0]     user_ttype;
304     (* mark_debug = "true" *)
305     wire  [7:0]     user_size;
306     (* mark_debug = "true" *)
307     wire [63:0]     user_data;
308     (* mark_debug = "true" *)
309     wire  [3:0]     user_hop;
310     (* mark_debug = "true" *)
311     wire [15:0]     dest_id;
312     (* mark_debug = "true" *)
313     wire [15:0]     source_id;
314     (* mark_debug = "true" *)
315     wireid_override;
316     (* mark_debug = "true" *)
317     wireregister_reset;
318     (* mark_debug = "true" *)
319     wirereset_all_registers;
320     (* mark_debug = "true" *)
321     wire  [3:0]     stats_address;
322     //(* mark_debug = "true" *)
323     //wire            send_pna;
324     //(* mark_debug = "true" *)
325     //wire  [2:0]     sent_pna_cause_lsb;
326     //(* mark_debug = "true" *)
327     //wire            in_recoverable_detect;
328     //(* mark_debug = "true" *)
329     //wire            in_retry_detect;
330     //(* mark_debug = "true" *)
331     //wire            out_recoverable_detect;
332     //(* mark_debug = "true" *)
333     //wire            out_fatal_detect;
334     
335     wirecore_sent_pna;
336     
337     wirecore_received_pna;
338     
339     wirecore_sent_pr;
340     
341     wirecore_received_pr;
342 
343     //Debug signals
344     wire            go_req   = peek_poke_go && user_ftype != 4'h8;
345     wire            go_maint = peek_poke_go && user_ftype == 4'h8;
346     wire            maint_inst = user_ttype == 4'h0;
347     reg   [63:0]    captured_data;
348     (* mark_debug = "true" *)
349     wirecontinuous_go;
350     regcontinuous_go_q;
351     regireq_autocheck_error_q;
352     regireq_request_done_q;
353     regreset_request_gen;
354     (* mark_debug = "true" *)
355     regcontinuous_in_process;
356     regreset_continuous_set;
357     (* mark_debug = "true" *)
358     regstop_continuous_test;
359     reg   [15:0]    reset_continuous_srl;
360     wire  [31:0]    stats_data;
361   //}}} End wire declarations ------------
362 
363 
364   //{{{ Drive LEDs to Development Board -------
365     assign led0[0] = 1'b1;
366     assign led0[1] = 1'b1;
367     assign led0[2] = !mode_1x;
368     assign led0[3] =port_initialized;
369     assign led0[4] =link_initialized;
370     assign led0[5] =clk_lock;
371     assign led0[6] = sim_train_en ? autocheck_error : 1'b0;
372     assign led0[7] = sim_train_en ? exercise_done : 1'b0;
373   //}}} End LEDs to Development Board ---------
374 
375     //assign send_pna               = phy_debug[0];
376     //assign sent_pna_cause_lsb     = phy_debug[34:32];
377     //assign in_recoverable_detect  = phy_debug[40];
378     //assign in_retry_detect        = phy_debug[39];
379     //assign out_recoverable_detect = phy_debug[38];
380     //assign out_fatal_detect       = phy_debug[37];
381     //assign send_pna               = phy_debug[0];
382     assign core_sent_pna     = phy_debug[160];
383     assign core_received_pna = phy_debug[161];
384     assign core_sent_pr      = phy_debug[162];
385     assign core_received_pr  = phy_debug[163];
386 
387 
388 
389 
390       assign continuous_go        = 1'b0;
391       assign peek_poke_go         = 1'b0;
392       assign user_addr            = 24'b0;
393       assign user_ftype           = 4'b0;
394       assign user_ttype           = 4'b0;
395       assign user_size            = 8'b0;
396       assign user_data            = 64'b0;
397       assign user_hop             = 4'b0;
398       assign dest_id              = 16'b0;
399       assign source_id            = 16'b0;
400       assign id_override          = 1'b0;
401       assign register_reset       = 1'b0;
402       assign reset_all_registers  = 1'b0;
403       assign stats_address        = 4'b0;
404 
405 
406 
407 
408   //feed back the last captured data to VIO
409   always @(posedge log_clk) begin
410     if (log_rst) begin
411       captured_data <= 64'h0;
412     //IO interface
413     end else if (iresp_tvalid && iresp_tready) begin
414       captured_data <=axis_iresp_tdata;
415     //maintenance interface
416     end else if (maintr_rvalid && maintr_rready) begin
417       captured_data <=axis_maintr_rdata;
418     end
419   end
420 
421   //Continuous data flow
422   always @(posedge log_clk) begin
423     continuous_go_q        <=continuous_go;
424     ireq_request_done_q    <=ireq_request_done;
425     ireq_autocheck_error_q <=ireq_autocheck_error;
426     reset_request_gen      <= sim_train_en ? log_rst : |reset_continuous_srl &&continuous_in_process;
427   end
428 
429   always @(posedge log_clk) begin
430     if (log_rst) begin
431       continuous_in_process <= 1'b0;
432     end else if (continuous_go && !continuous_go_q) begin
433       continuous_in_process <= 1'b1;
434     end else if (!continuous_go && continuous_go_q) begin
435       continuous_in_process <= 1'b0;
436     end
437   end
438   always @(posedge log_clk) begin
439     if (log_rst) begin
440       reset_continuous_set <= 1'b0;
441       stop_continuous_test <= 1'b0;
442     end else if (continuous_go && !continuous_go_q) begin
443       reset_continuous_set <= 1'b1;
444       stop_continuous_test <= 1'b0;
445     end else if (!ireq_autocheck_error_q && ireq_autocheck_error && continuous_in_process) begin
446       stop_continuous_test <= 1'b1;
447     end else if (!stop_continuous_test && !ireq_request_done_q && ireq_request_done &&
448                   continuous_in_process) begin
449       reset_continuous_set <= 1'b1;
450     end else begin
451       reset_continuous_set <= 1'b0;
452     end
453   end
454   always @(posedge log_clk) begin
455     if (log_rst) begin
456       reset_continuous_srl <= 16'h0;
457     end else if (reset_continuous_set) begin
458       reset_continuous_srl <= 16'hFFFF;
459     end else begin
460       reset_continuous_srl <= {reset_continuous_srl[14:0], 1'b0};
461     end
462   end
463 
464   //SRIO_DUT instantation -----------------
465   //for production and shared logic in the core
466 srio_gen2_0  srio_gen2_0_inst
467      (//---------------------------------------------------------------
468 .sys_clkp                (sys_clkp  ),
469 .sys_clkn                (sys_clkn  ),
470 .sys_rst                 (sys_rst   ),
471       //all clocks as output in shared logic mode
472 .log_clk_out             (log_clk   ),
473 .phy_clk_out             (phy_clk   ),
474 .gt_clk_out              (gt_clk    ),
475 .gt_pcs_clk_out          (gt_pcs_clk),
476 
477 .drpclk_out              (drpclk    ),
478 
479 .refclk_out              (refclk    ),
480 
481 .clk_lock_out            (clk_lock  ),
482       //all resets as output in shared logic mode
483 .log_rst_out             (log_rst   ),
484 .phy_rst_out             (phy_rst   ),
485 .buf_rst_out             (buf_rst   ),
486 .cfg_rst_out             (cfg_rst   ),
487 .gt_pcs_rst_out          (gt_pcs_rst),
488 
489 //---------------------------------------------------------------
490 
491 .gt0_qpll_clk_out           (gt0_qpll_clk_out       ),
492 .gt0_qpll_out_refclk_out    (gt0_qpll_out_refclk_out),
493 
494 
495 
496 // //---------------------------------------------------------------
497 .srio_rxn0               (srio_rxn0),
498 .srio_rxp0               (srio_rxp0),
499 
500 .srio_txn0               (srio_txn0),
501 .srio_txp0               (srio_txp0),
502 
503 .s_axis_ireq_tvalid            (ireq_tvalid),
504 .s_axis_ireq_tready            (ireq_tready),
505 .s_axis_ireq_tlast             (ireq_tlast),
506 .s_axis_ireq_tdata             (ireq_tdata),
507 .s_axis_ireq_tkeep             (ireq_tkeep),
508 .s_axis_ireq_tuser             (ireq_tuser),
509 
510 .m_axis_iresp_tvalid           (iresp_tvalid),
511 .m_axis_iresp_tready           (iresp_tready),
512 .m_axis_iresp_tlast            (iresp_tlast),
513 .m_axis_iresp_tdata            (iresp_tdata),
514 .m_axis_iresp_tkeep            (iresp_tkeep),
515 .m_axis_iresp_tuser            (iresp_tuser),
516 
517 .s_axis_tresp_tvalid           (tresp_tvalid),
518 .s_axis_tresp_tready           (tresp_tready),
519 .s_axis_tresp_tlast            (tresp_tlast),
520 .s_axis_tresp_tdata            (tresp_tdata),
521 .s_axis_tresp_tkeep            (tresp_tkeep),
522 .s_axis_tresp_tuser            (tresp_tuser),
523 
524 .m_axis_treq_tvalid            (treq_tvalid),
525 .m_axis_treq_tready            (treq_tready),
526 .m_axis_treq_tlast             (treq_tlast),
527 .m_axis_treq_tdata             (treq_tdata),
528 .m_axis_treq_tkeep             (treq_tkeep),
529 .m_axis_treq_tuser             (treq_tuser),
530 
531 .s_axi_maintr_rst              (maintr_rst),
532 
533 .s_axi_maintr_awvalid          (maintr_awvalid),
534 .s_axi_maintr_awready          (maintr_awready),
535 .s_axi_maintr_awaddr           (maintr_awaddr),
536 .s_axi_maintr_wvalid           (maintr_wvalid),
537 .s_axi_maintr_wready           (maintr_wready),
538 .s_axi_maintr_wdata            (maintr_wdata),
539 .s_axi_maintr_bvalid           (maintr_bvalid),
540 .s_axi_maintr_bready           (maintr_bready),
541 .s_axi_maintr_bresp            (maintr_bresp),
542 
543 .s_axi_maintr_arvalid          (maintr_arvalid),
544 .s_axi_maintr_arready          (maintr_arready),
545 .s_axi_maintr_araddr           (maintr_araddr),
546 .s_axi_maintr_rvalid           (maintr_rvalid),
547 .s_axi_maintr_rready           (maintr_rready),
548 .s_axi_maintr_rdata            (maintr_rdata),
549 .s_axi_maintr_rresp            (maintr_rresp),
550 
551 .sim_train_en                  (sim_train_en),
552 .phy_mce                       (phy_mce),
553 .phy_link_reset                (phy_link_reset),
554 .force_reinit                  (force_reinit),
555 
556 
557 .phy_rcvd_mce                  (phy_rcvd_mce       ),
558 .phy_rcvd_link_reset           (phy_rcvd_link_reset),
559 .phy_debug                     (phy_debug          ),
560 .gtrx_disperr_or               (gtrx_disperr_or    ),
561 .gtrx_notintable_or            (gtrx_notintable_or ),
562 
563 .port_error                    (port_error         ),
564 .port_timeout                  (port_timeout       ),
565 .srio_host                     (srio_host          ),
566 .port_decode_error             (port_decode_error  ),
567 .deviceid                      (deviceid           ),
568 .idle2_selected                (idle2_selected     ),
569       .phy_lcl_master_enable_out     (), //these are side band output only signals
570 .buf_lcl_response_only_out     (),
571 .buf_lcl_tx_flow_control_out   (),
572 .buf_lcl_phy_buf_stat_out      (),
573 .phy_lcl_phy_next_fm_out       (),
574 .phy_lcl_phy_last_ack_out      (),
575 .phy_lcl_phy_rewind_out        (),
576 .phy_lcl_phy_rcvd_buf_stat_out (),
577 .phy_lcl_maint_only_out        (),
578 //---
579 
580 
581 
582 
583 
584 //---
585 .port_initialized              (port_initialized  ),
586 .link_initialized              (link_initialized  ),
587 .idle_selected                 (idle_selected     ),
588 .mode_1x                       (mode_1x           )
589 );
590   //End of SRIO_DUT instantiation ---------
591 
592 
593   //Initiator-driven side --------------------
594 
595 
596   //{{{ IREQ Interface ---------------------------
597   //Select between internally-driven sequences or user sequences
598   assign ireq_tvalid = (VALIDATION_FEATURES) ?val_ireq_tvalid : axis_ireq_tvalid;
599   assign ireq_tlast  = (VALIDATION_FEATURES) ?val_ireq_tlast  : axis_ireq_tlast;
600   assign ireq_tdata  = (VALIDATION_FEATURES) ?val_ireq_tdata  : axis_ireq_tdata;
601   assign ireq_tkeep  = (VALIDATION_FEATURES) ?val_ireq_tkeep  : axis_ireq_tkeep;
602   assign ireq_tuser  = (VALIDATION_FEATURES) ?val_ireq_tuser  : axis_ireq_tuser;
603 
604   assign axis_ireq_tready = (!VALIDATION_FEATURES) &&ireq_tready;
605   assign val_ireq_tready  = (VALIDATION_FEATURES)  &&ireq_tready;
606 
607 
608 
609 
610   //When enabled, report results.
611   //This is a simulation-only option and cannot be synthesized
612   generate if (SIM_VERBOSE) begin: ireq_reporting_gen
613 srio_report
614      #(.VERBOSITY        (2),
615        .DIRECTION        (1),
616        .NAME             (0))  //Data is flowing into the core
617 srio_ireq_report_inst
618 (
619 .log_clk                 (log_clk),
620 .log_rst                 (log_rst),
621 
622 .tvalid                  (ireq_tvalid),
623 .tready                  (ireq_tready),
624 .tlast                   (ireq_tlast),
625 .tdata                   (ireq_tdata),
626 .tkeep                   (ireq_tkeep),
627 .tuser                   (ireq_tuser)
628 );
629   end
630   endgenerate
631   //}}} End of IREQ Interface --------------------
632 
633 
634   //{{{ Initiator Generator/Checker --------------
635 
636   //If internally-driven sequences are required
637   generate if (VALIDATION_FEATURES) begin: ireq_validation_gen
638 srio_request_gen_srio_gen2_0
639      #(.SEND_SWRITE       (1),
640        .SEND_NWRITER      (1),
641        .SEND_NWRITE       (1),
642        .SEND_NREAD        (1),
643        .SEND_FTYPE9       (0),
644        .SEND_DB           (1),
645        .SEND_MSG          (1))
646 srio_request_gen_inst (
647 .log_clk                 (log_clk),
648 .log_rst                 (reset_request_gen),
649 
650 .deviceid                (deviceid),
651 .dest_id                 (dest_id),
652 .source_id               (source_id),
653 .id_override             (id_override),
654 
655 .val_ireq_tvalid         (val_ireq_tvalid),
656 .val_ireq_tready         (val_ireq_tready),
657 .val_ireq_tlast          (val_ireq_tlast),
658 .val_ireq_tdata          (val_ireq_tdata),
659 .val_ireq_tkeep          (val_ireq_tkeep),
660 .val_ireq_tuser          (val_ireq_tuser),
661 
662 .val_iresp_tvalid        (val_iresp_tvalid),
663 .val_iresp_tready        (val_iresp_tready),
664 .val_iresp_tlast         (val_iresp_tlast),
665 .val_iresp_tdata         (val_iresp_tdata),
666 .val_iresp_tkeep         (val_iresp_tkeep),
667 .val_iresp_tuser         (val_iresp_tuser),
668 
669 .link_initialized        (link_initialized),
670 
671       //use these ports to peek/poke IO transactions
672 .go                      (go_req),
673       .user_addr               ({10'h000, user_addr}),
674 .user_ftype              (user_ftype),
675 .user_ttype              (user_ttype),
676 .user_size               (user_size),
677 .user_data               (user_data),
678 
679 .request_autocheck_error (ireq_autocheck_error),
680 .request_done            (ireq_request_done)
681 );
682   end
683   endgenerate
684   //}}} End of Initiator Generator/Checker -------
685 
686 
687   //{{{ IRESP Interface --------------------------
688   //Select between internally-driven sequences or user sequences
689 
690   assign iresp_tready = (VALIDATION_FEATURES) ?val_iresp_tready : axis_iresp_tready;
691 
692   assign val_iresp_tvalid  = (VALIDATION_FEATURES) &&iresp_tvalid;
693   assign val_iresp_tlast   =iresp_tlast;
694   assign val_iresp_tdata   =iresp_tdata;
695   assign val_iresp_tkeep   =iresp_tkeep;
696   assign val_iresp_tuser   =iresp_tuser;
697 
698   assign axis_iresp_tvalid = (!VALIDATION_FEATURES) &&iresp_tvalid;
699   assign axis_iresp_tlast  =iresp_tlast;
700   assign axis_iresp_tdata  =iresp_tdata;
701   assign axis_iresp_tkeep  =iresp_tkeep;
702   assign axis_iresp_tuser  =iresp_tuser;
703 
704 
705   //When enabled, report results.
706   //This is a simulation-only option and cannot be synthesized
707   generate if (SIM_VERBOSE) begin: iresp_reporting_gen
708 srio_report
709      #(.VERBOSITY              (2),
710        .DIRECTION              (0),
711        .NAME                   (1))  //Data is flowing out of the core
712 srio_iresp_report_inst
713 (
714 .log_clk                 (log_clk),
715 .log_rst                 (log_rst),
716 
717 .tvalid                  (iresp_tvalid),
718 .tready                  (iresp_tready),
719 .tlast                   (iresp_tlast),
720 .tdata                   (iresp_tdata),
721 .tkeep                   (iresp_tkeep),
722 .tuser                   (iresp_tuser)
723 );
724   end
725   endgenerate
726   //}}} End of IRESP Interface -------------------
727 
728 
729 
730 
731 
732   assign autocheck_error         = ireq_autocheck_error ||maint_autocheck_error;
733   assign exercise_done           = ireq_request_done &&maint_done;
734 
735   //}}} End of Initiator-driven side -------------
736 
737 
738   //{{{ Target-driven side -----------------------
739 
740   //{{{ TRESP Interface --------------------------
741   //Select between internally-driven sequences or user sequences
742   assign tresp_tvalid = (VALIDATION_FEATURES) ?val_tresp_tvalid : axis_tresp_tvalid;
743   assign tresp_tlast  = (VALIDATION_FEATURES) ?val_tresp_tlast  : axis_tresp_tlast;
744   assign tresp_tdata  = (VALIDATION_FEATURES) ?val_tresp_tdata  : axis_tresp_tdata;
745   assign tresp_tkeep  = (VALIDATION_FEATURES) ?val_tresp_tkeep  : axis_tresp_tkeep;
746   assign tresp_tuser  = (VALIDATION_FEATURES) ?val_tresp_tuser  : axis_tresp_tuser;
747 
748   assign axis_tresp_tready = (!VALIDATION_FEATURES) &&tresp_tready;
749   assign val_tresp_tready  = (VALIDATION_FEATURES)  &&tresp_tready;
750 
751 
752   //When enabled, report results.
753   //This is a simulation-only option and cannot be synthesized
754   generate if (SIM_VERBOSE) begin: tresp_reporting_gen
755 srio_report
756      #(.VERBOSITY              (2),
757        .DIRECTION              (1),
758        .NAME                   (8))  //Data is flowing into the core
759 srio_tresp_report_inst
760 (
761 .log_clk                 (log_clk),
762 .log_rst                 (log_rst),
763 
764 .tvalid                  (tresp_tvalid),
765 .tready                  (tresp_tready),
766 .tlast                   (tresp_tlast),
767 .tdata                   (tresp_tdata),
768 .tkeep                   (tresp_tkeep),
769 .tuser                   (tresp_tuser)
770 );
771   end
772   endgenerate
773   //}}} End of TRESP Interface -------------------
774 
775 
776   //{{{ Target Generator/Checker -----------------
777 
778   //If internally-driven sequences are required
779   generate if (VALIDATION_FEATURES) begin: tresp_validation_gen
780 srio_response_gen_srio_gen2_0 srio_response_gen_inst (
781 .log_clk                 (log_clk),
782 .log_rst                 (log_rst),
783 
784 .deviceid                (deviceid),
785 .source_id               (source_id),
786 .id_override             (id_override),
787 
788 .val_tresp_tvalid        (val_tresp_tvalid),
789 .val_tresp_tready        (val_tresp_tready),
790 .val_tresp_tlast         (val_tresp_tlast),
791 .val_tresp_tdata         (val_tresp_tdata),
792 .val_tresp_tkeep         (val_tresp_tkeep),
793 .val_tresp_tuser         (val_tresp_tuser),
794 
795 .val_treq_tvalid         (val_treq_tvalid),
796 .val_treq_tready         (val_treq_tready),
797 .val_treq_tlast          (val_treq_tlast),
798 .val_treq_tdata          (val_treq_tdata),
799 .val_treq_tkeep          (val_treq_tkeep),
800 .val_treq_tuser          (val_treq_tuser)
801 );
802   end
803   endgenerate
804   //}}} End of Target Generator/Checker ----------
805 
806 
807   //{{{ TREQ Interface ---------------------------
808   //Select between internally-driven sequences or user sequences
809 
810   assign treq_tready = (VALIDATION_FEATURES) ?val_treq_tready : axis_treq_tready;
811 
812   assign val_treq_tvalid  = (VALIDATION_FEATURES) &&treq_tvalid;
813   assign val_treq_tlast   =treq_tlast;
814   assign val_treq_tdata   =treq_tdata;
815   assign val_treq_tkeep   =treq_tkeep;
816   assign val_treq_tuser   =treq_tuser;
817 
818   assign axis_treq_tvalid = (!VALIDATION_FEATURES) &&treq_tvalid;
819   assign axis_treq_tlast  =treq_tlast;
820   assign axis_treq_tdata  =treq_tdata;
821   assign axis_treq_tkeep  =treq_tkeep;
822   assign axis_treq_tuser  =treq_tuser;
823 
824 
825   //When enabled, report results.
826   //This is a simulation-only option and cannot be synthesized
827   generate if (SIM_VERBOSE) begin: treq_reporting_gen
828 srio_report
829      #(.VERBOSITY              (2),
830        .DIRECTION              (0),
831        .NAME                   (9))  //Data is flowing out of the core
832 srio_treq_report_inst
833 (
834 .log_clk                 (log_clk),
835 .log_rst                 (log_rst),
836 
837 .tvalid                  (treq_tvalid),
838 .tready                  (treq_tready),
839 .tlast                   (treq_tlast),
840 .tdata                   (treq_tdata),
841 .tkeep                   (treq_tkeep),
842 .tuser                   (treq_tuser)
843 );
844   end
845   endgenerate
846   //}}} End of TREQ Interface --------------------
847 
848 
849 
850 
851 
852   //}}} End of Target-driven side ----------------
853 
854   //{{{ Maintenance Interface --------------------
855 
856   //Select between internally-driven sequences or user sequences
857   assign maintr_awvalid = (QUICK_STARTUP) ?val_maintr_awvalid : axis_maintr_awvalid;
858   assign maintr_awaddr  = (QUICK_STARTUP) ?val_maintr_awaddr  : axis_maintr_awaddr;
859   assign maintr_wvalid  = (QUICK_STARTUP) ?val_maintr_wvalid  : axis_maintr_wvalid;
860   assign maintr_wdata   = (QUICK_STARTUP) ?val_maintr_wdata   : axis_maintr_wdata;
861   assign maintr_bready  = (QUICK_STARTUP) ?val_maintr_bready  : axis_maintr_bready;
862 
863   assign maintr_arvalid = (QUICK_STARTUP) ?val_maintr_arvalid : axis_maintr_arvalid;
864   assign maintr_araddr  = (QUICK_STARTUP) ?val_maintr_araddr  : axis_maintr_araddr;
865   assign maintr_rready  = (QUICK_STARTUP) ?val_maintr_rready  : axis_maintr_rready;
866 
867 
868   assign axis_maintr_awready = (!QUICK_STARTUP) &&maintr_awready;
869   assign axis_maintr_wready = (!QUICK_STARTUP) &&maintr_wready;
870   assign axis_maintr_bvalid = (!QUICK_STARTUP) &&maintr_bvalid;
871   assign axis_maintr_bresp =maintr_bresp;
872 
873   assign axis_maintr_arready = (!QUICK_STARTUP) &&maintr_arready;
874   assign axis_maintr_rvalid = (!QUICK_STARTUP) &&maintr_rvalid;
875   assign axis_maintr_rdata =maintr_rdata;
876   assign axis_maintr_rresp =maintr_rresp;
877 
878   assign val_maintr_awready = (QUICK_STARTUP) &&maintr_awready;
879   assign val_maintr_wready = (QUICK_STARTUP) &&maintr_wready;
880   assign val_maintr_bvalid = (QUICK_STARTUP) &&maintr_bvalid;
881   assign val_maintr_bresp =maintr_bresp;
882 
883   assign val_maintr_arready = (QUICK_STARTUP) &&maintr_arready;
884   assign val_maintr_rvalid = (QUICK_STARTUP) &&maintr_rvalid;
885   assign val_maintr_rdata =maintr_rdata;
886   assign val_maintr_rresp =maintr_rresp;
887 
888 
889   //If internally-driven sequences are required
890   generate if (QUICK_STARTUP) begin: quick_maint_gen
891 srio_quick_start_srio_gen2_0 srio_quick_start_inst (
892 .log_clk                 (log_clk),
893 .log_rst                 (log_rst),
894 
895 .maintr_awvalid          (val_maintr_awvalid),
896 .maintr_awready          (val_maintr_awready),
897 .maintr_awaddr           (val_maintr_awaddr),
898 .maintr_wvalid           (val_maintr_wvalid),
899 .maintr_wready           (val_maintr_wready),
900 .maintr_wdata            (val_maintr_wdata),
901 .maintr_bvalid           (val_maintr_bvalid),
902 .maintr_bready           (val_maintr_bready),
903 .maintr_bresp            (val_maintr_bresp),
904 
905 .maintr_arvalid          (val_maintr_arvalid),
906 .maintr_arready          (val_maintr_arready),
907 .maintr_araddr           (val_maintr_araddr),
908 .maintr_rvalid           (val_maintr_rvalid),
909 .maintr_rready           (val_maintr_rready),
910 .maintr_rdata            (val_maintr_rdata),
911 .maintr_rresp            (val_maintr_rresp),
912 
913       //use these ports to peek/poke maintenance transactions
914 .go                      (go_maint),
915 .user_hop                (user_hop),
916 .user_inst               (maint_inst),
917 .user_addr               (user_addr),
918       .user_data               (user_data[31:0]),
919 
920 .link_initialized        (link_initialized),
921 .maint_done              (maint_done),
922 .maint_autocheck_error   (maint_autocheck_error)
923 );
924   end else begin: no_quick_maint_gen
925     assign maintr_awaddr         = 32'h0;
926     assign maintr_wvalid         = 1'b0;
927     assign maintr_wdata          = 32'h0;
928     assign maintr_bready         = 1'b0;
929     assign maintr_arvalid        = 1'b0;
930     assign maintr_araddr         = 32'h0;
931     assign maintr_rready         = 1'b0;
932     assign maint_done            = 1'b1;
933     assign maint_autocheck_error = 1'b0;
934   end
935   endgenerate
936 
937   //}}} End of Maintenance Interface -------------
938 
939 
940   //{{{ Statistics Gatherer ----------------------
941 
942   //When enabled, statistics gatherer collects details about performance.
943   //This module is synthesizable and may be accessed through Chipscope
944   generate if (STATISTICS_GATHERING) begin: stats_gen
945 srio_statistics_srio_gen2_0 srio_statistics_inst (
946 .log_clk                 (log_clk),
947 .phy_clk                 (phy_clk),
948 .gt_pcs_clk              (gt_pcs_clk),
949 .log_rst                 (log_rst),
950 .phy_rst                 (phy_rst),
951 
952       //outgoing port 1
953 .tvalid_o1                  (ireq_tvalid),
954 .tready_o1                  (ireq_tready),
955 .tlast_o1                   (ireq_tlast),
956 .tdata_o1                   (ireq_tdata),
957 
958       //outgoing port 2
959 .tvalid_o2                  (iresp_tvalid),
960 .tready_o2                  (iresp_tready),
961 .tlast_o2                   (iresp_tlast),
962 .tdata_o2                   (iresp_tdata),
963 
964       //incoming port 1
965 .tvalid_i1                  (treq_tvalid),
966 .tready_i1                  (treq_tready),
967 .tlast_i1                   (treq_tlast),
968 .tdata_i1                   (treq_tdata),
969 
970       //incoming port 2
971 .tvalid_i2                  (tresp_tvalid),
972 .tready_i2                  (tresp_tready),
973 .tlast_i2                   (tresp_tlast),
974 .tdata_i2                   (tresp_tdata),
975 
976 .link_initialized        (link_initialized),
977 .phy_debug               (phy_debug),
978 .gtrx_disperr_or         (gtrx_disperr_or),
979 .gtrx_notintable_or      (gtrx_notintable_or),
980 
981 .register_reset          (register_reset),
982 .reset_all_registers     (reset_all_registers),
983 .stats_address           (stats_address),
984 
985 .stats_data              (stats_data)
986 );
987   end
988   endgenerate
989 
990   //}}} End of Statistics Gatherer ---------------
991 
992 endmodule

1 //
2 //(c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
3 //
4 //                                                                 
5 //This file contains confidential and proprietary information
6 //of Xilinx, Inc. and is protected under U.S. and
7 //international copyright and other intellectual property
8 //laws.
9 // 
10 //DISCLAIMER
11 //This disclaimer is not a license and does not grant any
12 //rights to the materials distributed herewith. Except as
13 //otherwise provided in a valid license issued to you by
14 //Xilinx, and to the maximum extent permitted by applicable
15 //law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16 //WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17 //AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18 //BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19 //INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20 //(2) Xilinx shall not be liable (whether in contract or tort,
21 //including negligence, or under any other theory of
22 //liability) for any loss or damage of any kind or nature
23 //related to, arising under or in connection with these
24 //materials, including for any direct, or any indirect,
25 //special, incidental, or consequential loss or damage
26 //(including loss of data, profits, goodwill, or any type of
27 //loss or damage suffered as a result of any action brought
28 //by a third party) even if such damage or loss was
29 //reasonably foreseeable or Xilinx had been advised of the
30 //possibility of the same.
31 // 
32 //CRITICAL APPLICATIONS
33 //Xilinx products are not designed or intended to be fail-
34 //safe, or for use in any application requiring fail-safe
35 //performance, such as life-support or safety devices or
36 //systems, Class III medical devices, nuclear facilities,
37 //applications related to the deployment of airbags, or any
38 //other applications that could lead to death, personal
39 //injury, or severe property or environmental damage
40 //(individually and collectively, "Critical
41 //Applications"). Customer assumes the sole risk and
42 //liability of any use of Xilinx products in Critical
43 //Applications, subject only to applicable laws and
44 //regulations governing limitations on product liability.
45 // 
46 //THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47 //PART OF THIS FILE AT ALL TIMES.                                
48 `timescale 1ps/1ps
49 
50 modulesrio_request_gen_srio_gen2_0
51 #(
52     parameter     SEND_SWRITE   = 0,
53     parameter     SEND_NWRITER  = 0,
54     parameter     SEND_NWRITE   = 0,
55     parameter     SEND_NREAD    = 0,
56     parameter     SEND_DB       = 0,
57     parameter     SEND_FTYPE9   = 0,
58     parameter     SEND_MSG      = 0)
59 (
60     inputlog_clk,
61     inputlog_rst,
62 
63     input      [15:0] deviceid,
64     input      [15:0] dest_id,
65     input      [15:0] source_id,
66     inputid_override,
67 
68     output regval_ireq_tvalid,
69     inputval_ireq_tready,
70     output regval_ireq_tlast,
71     output reg [63:0] val_ireq_tdata,
72     output      [7:0] val_ireq_tkeep,
73     output     [31:0] val_ireq_tuser,
74 
75     inputval_iresp_tvalid,
76     output regval_iresp_tready,
77     inputval_iresp_tlast,
78     input      [63:0] val_iresp_tdata,
79     input       [7:0] val_iresp_tkeep,
80     input      [31:0] val_iresp_tuser,
81 
82     inputlink_initialized,
83     inputgo,
84     input      [33:0] user_addr,
85     input       [3:0] user_ftype,
86     input       [3:0] user_ttype,
87     input       [7:0] user_size,
88     input      [63:0] user_data,
89 
90     output regrequest_autocheck_error,
91     output regrequest_done
92 );
93 
94   //{{{ local parameters -----------------
95 
96   localparam [3:0] NREAD  = 4'h2;
97   localparam [3:0] NWRITE = 4'h5;
98   localparam [3:0] SWRITE = 4'h6;
99   localparam [3:0] DOORB  = 4'hA;
100   localparam [3:0] MESSG  = 4'hB;
101   localparam [3:0] RESP   = 4'hD;
102   localparam [3:0] FTYPE9 = 4'h9;
103 
104   localparam [3:0] TNWR   = 4'h4;
105   localparam [3:0] TNWR_R = 4'h5;
106   localparam [3:0] TNRD   = 4'h4;
107 
108   localparam [3:0] TNDATA = 4'h0;
109   localparam [3:0] MSGRSP = 4'h1;
110   localparam [3:0] TWDATA = 4'h8;
111 
112   //}}} End local parameters -------------
113 
114 
115   //{{{ wire declarations ----------------
116   reg  [15:0] log_rst_shift;
117   wire        log_rst_q = log_rst_shift[15];
118 
119   //synthesis attribute ram_style of instruction is distributed
120   wire [63:0] instruction [0:511];
121   `include "instruction_list.vh"
122 
123   reg  [12:0] link_initialized_cnt;
124   wire        link_initialized_delay = link_initialized_cnt[12];
125 
126   wire        ireq_advance_condition  = val_ireq_tready &&val_ireq_tvalid;
127   wire        iresp_advance_condition = val_iresp_tready &&val_iresp_tvalid;
128 
129   //request side
130   wire [63:0] request_data_out;
131   reg  [47:0] request_data_out_q; //upper 63:48 unused
132   regauto_advance_data;
133   reg   [8:0] request_address;
134 
135   wire [15:0] src_id;
136   wire  [1:0] prio;
137   wire  [7:0] tid;
138   wire [35:0] srio_addr;
139   wire [63:0] header_beat;
140 
141   wire  [3:0] current_ftype;
142   wire  [3:0] current_ttype;
143   wire  [7:0] current_size;
144   wire  [15:0] current_size_ftype9;
145   wire  [4:0] number_of_data_beats;
146   wire  [12:0] number_of_data_beats_ftype9;
147   reg   [4:0] number_of_data_beats_q;
148   reg   [12:0] number_of_data_beats_q_ftype9;
149   reg   [5:0] current_beat_cnt;
150   reg   [13:0] current_beat_cnt_ftype9;
151 
152   reglast_packet_beat_q, last_packet_beat_qq, last_packet_beat_qqq;
153   reg   [7:0] data_beat, data_beat_q;
154   reg  [15:0] instruction_cnt;
155   regsent_all_packets;
156 
157   reggo_q;
158 
159   //response check side
160   regexpecting_a_response;
161   reg   [8:0] write_queue_addr;
162   reg   [8:0] read_queue_addr;
163   wire [63:0] write_queue_data_d;
164   reg  [63:0] write_queue_data;
165   wire [63:0] read_queue_data;
166   reg  [63:0] read_queue_data_q;
167   regcompare_received;
168   wire  [3:0] expected_ftype;
169   wire  [7:0] expected_tid;
170   wire  [7:0] expected_size;
171   regdelay_assert_tready;
172 
173   //}}} End wire declarations ------------
174 
175 
176   //{{{ Common-use Signals ---------------
177   //Initialize instruction list
178   genvarii;
179   generate
180     for (ii = 0; ii < 512; ii = ii + 1) begin: instruction_gen
181         //Load SWRITEs
182         if(ii < NUM_SWRITES) begin
183          assign instruction[ii] = swrite_instruction[(ii+1)*64-1:ii*64];
184         //Load NWRITE_Rs
185         end else if(ii < (NUM_SWRITES + NUM_NWRITERS)) begin
186          assign  instruction[ii] = nwriter_instruction[(ii-NUM_SWRITES+1)*64-1:(ii-NUM_SWRITES)*64];
187         //Load NWRITEs
188         end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES)) begin
189          assign  instruction[ii] = nwrite_instruction[(ii-NUM_SWRITES-NUM_NWRITERS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS)*64];
190         //Load NREADs
191         end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS)) begin
192          assign  instruction[ii] = nread_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES)*64];
193         //Load DBs
194         end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS)) begin
195          assign  instruction[ii] = db_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS)*64];
196         //Load MSGs
197         end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS)) begin
198          assign  instruction[ii] = msg_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS)*64];
199         end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS + NUM_FTYPE9)) begin
200          assign  instruction[ii] = ftype9_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS-NUM_MSGS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS-NUM_MSGS)*64];
201         end else begin
202          assign  instruction[ii] = 64'h0;
203         end
204     end
205   endgenerate
206 
207   //Simple Assignments
208   assign val_ireq_tkeep  = 8'hFF;
209   assign src_id          = id_override ?source_id : deviceid;
210   assign prio            = 2'h1;
211   assign val_ireq_tuser  ={src_id, dest_id};
212   assign tid             = request_address[7:0];
213   assign srio_addr       = go ? user_addr : request_data_out_q[43:8];
214   assign current_ftype   = go ? user_ftype : request_data_out[51:48];
215   assign current_ttype   = go ? user_ttype : request_data_out_q[47:44];
216   assign current_size    = go ? user_size : request_data_out_q[7:0];
217   assign current_size_ftype9    = go ? {user_size,user_size} : request_data_out_q[23:8];
218   //                        //Fixed CR# 799600, 12/15/2014, Added ftype switch for message in below header in place of plain "tid" field.
219   assign header_beat     = {((current_ftype == MESSG)? request_data_out[59:52] : tid), current_ftype, current_ttype, 1'b0, prio, 1'b0, current_size, srio_addr};
220   //End Simple Assignments
221 
222   always @(posedge log_clk or posedge log_rst) begin
223     if(log_rst)
224       log_rst_shift <= 16'hFFFF;
225     else
226       log_rst_shift <= {log_rst_shift[14:0], 1'b0};
227   end
228 
229   always @(posedge log_clk) begin
230     if (log_rst_q) begin
231       last_packet_beat_q       <= 1'b1;
232       last_packet_beat_qq      <= 1'b1;
233       last_packet_beat_qqq     <= 1'b1;
234       number_of_data_beats_q   <= 5'h0;
235       number_of_data_beats_q_ftype9   <= 13'h0;
236       read_queue_data_q        <= 64'h0;
237       go_q                     <= 1'b0;
238     end else begin
239       last_packet_beat_q       <= ireq_advance_condition &&val_ireq_tlast;
240       last_packet_beat_qq      <=last_packet_beat_q;
241       last_packet_beat_qqq     <= last_packet_beat_qq || !link_initialized_delay;
242       number_of_data_beats_q   <=number_of_data_beats;
243       number_of_data_beats_q_ftype9   <=number_of_data_beats_ftype9;
244       read_queue_data_q        <=read_queue_data;
245       go_q                     <=go;
246     end
247   end
248 
249 
250   //put a sufficient delay on the initialization to improve simulation time.
251   //Not needed for actual hardware but does no damage if kept.
252   always @(posedge log_clk) begin
253     if (log_rst_q) begin
254       link_initialized_cnt <= 0;
255     end else if (link_initialized && !link_initialized_delay) begin
256       link_initialized_cnt <= link_initialized_cnt + 1'b1;
257     end else if (!link_initialized) begin
258       link_initialized_cnt <= 0;
259     end
260   end
261 
262   //}}} End Common-use Signals -----------
263 
264 
265   //{{{ Request Packet Formatter ---------
266   assign number_of_data_beats = current_beat_cnt == 0 ? current_size[7:3] : number_of_data_beats_q;
267 
268   assign number_of_data_beats_ftype9 = current_beat_cnt_ftype9 == 0 ? current_size_ftype9[15:3] : number_of_data_beats_q_ftype9;
269 
270   always @(posedge log_clk) begin
271     if (log_rst_q) begin
272       current_beat_cnt <= 6'h0;
273     end else if (ireq_advance_condition && val_ireq_tlast) begin
274       current_beat_cnt <= 6'h0;
275     end else if (ireq_advance_condition) begin
276       current_beat_cnt <= current_beat_cnt + 1'b1;
277     end
278   end
279 
280   always @(posedge log_clk) begin
281     if (log_rst_q) begin
282       current_beat_cnt_ftype9 <= 14'h000;
283     end else if (ireq_advance_condition && val_ireq_tlast) begin
284       current_beat_cnt_ftype9 <= 14'h000;
285     end else if (ireq_advance_condition) begin
286       current_beat_cnt_ftype9 <= current_beat_cnt_ftype9 + 1'b1;
287     end
288   end
289 
290 wire [13:0] extended_number_of_data_beats_ftype9;
291 
292 assign extended_number_of_data_beats_ftype9 = {1'b0, number_of_data_beats_ftype9};
293 
294   always @(posedge log_clk) begin
295     if (log_rst_q) begin
296       val_ireq_tlast  <= 1'b0;
297     end else if (((current_ftype == NREAD) || (current_ftype == DOORB)) && current_beat_cnt == 6'h00) begin 
298       val_ireq_tlast  <= !(ireq_advance_condition &&val_ireq_tlast);
299     end else if ((current_beat_cnt == {1'b0, number_of_data_beats} && ireq_advance_condition && (current_ftype != FTYPE9)) || ((current_beat_cnt_ftype9 == extended_number_of_data_beats_ftype9) && ireq_advance_condition && (current_ftype == FTYPE9) )) begin
300       val_ireq_tlast  <= !val_ireq_tlast;
301     end else if (!val_ireq_tready) begin
302       val_ireq_tlast  <=val_ireq_tlast;
303     end else if (val_ireq_tready || !val_ireq_tvalid) begin
304       val_ireq_tlast  <= 1'b0;
305     end
306   end
307   always @(posedge log_clk) begin
308     if ((current_beat_cnt == 0 && !ireq_advance_condition && (current_ftype != FTYPE9)) || (current_beat_cnt_ftype9 == 0 && !ireq_advance_condition && (current_ftype == FTYPE9))) begin
309       val_ireq_tdata  <=header_beat;
310     end else if (go) begin
311       val_ireq_tdata  <=user_data;
312     end else begin
313       val_ireq_tdata  <= {8{data_beat}};
314     end
315   end
316   always @* begin
317     data_beat =data_beat_q;
318     if (ireq_advance_condition && current_beat_cnt != 0) begin
319       data_beat = data_beat_q + 1'b1;
320     end
321   end
322   always @(posedge log_clk) begin
323     if (log_rst_q) begin
324       data_beat_q <= 8'h00;
325     end else begin
326       data_beat_q <=data_beat;
327     end
328   end
329 
330   always @(posedge log_clk) begin
331     if (log_rst_q) begin
332       val_ireq_tvalid  <= 1'b0;
333       instruction_cnt  <= 16'h0;
334       sent_all_packets <= 1'b0;
335     end else if (link_initialized_delay && instruction_cnt < NUMBER_OF_INSTRUCTIONS && last_packet_beat_qqq) begin
336       val_ireq_tvalid  <= 1'b1;
337     end else if (ireq_advance_condition && val_ireq_tlast) begin
338       val_ireq_tvalid  <= 1'b0;
339       instruction_cnt  <= instruction_cnt + 1'b1;
340     end else if (go && !go_q) begin
341       val_ireq_tvalid  <= 1'b1;
342     end else if (instruction_cnt == NUMBER_OF_INSTRUCTIONS) begin
343       sent_all_packets <= 1'b1;
344     end
345   end
346 
347   //}}} End Request Packet Formatter -----
348 
349 
350   //{{{ Request Data Storage -------------
351   always @(posedge log_clk) begin
352     if (log_rst_q) begin
353       request_address <= 9'h0;
354     end else if ((ireq_advance_condition && current_beat_cnt == 0 && (current_ftype != FTYPE9)) || ((current_beat_cnt_ftype9 == extended_number_of_data_beats_ftype9) && ireq_advance_condition && (current_ftype == FTYPE9))) begin
355       request_address <= request_address + 1'b1;
356     end
357   end
358 
359   assign request_data_out =instruction[request_address];
360 
361   always @ (posedge log_clk) begin
362     if (ireq_advance_condition || auto_advance_data ||last_packet_beat_qq)
363       request_data_out_q <= request_data_out[47:0];
364   end
365   always @ (posedge log_clk) begin
366     if (log_rst_q) begin
367       auto_advance_data <= 1'b1;
368     end else if (ireq_advance_condition) begin
369       auto_advance_data <= 1'b0;
370     end
371   end
372   //}}} End of Request Data Storage ------
373 
374 
375   //{{{ Response Queue -------------------
376 
377   assign write_queue_data_d = {44'h0, tid, current_ftype, current_size};
378   always @ (posedge log_clk) begin
379     write_queue_data <=write_queue_data_d;
380   end
381 
382 RAMB36SDP #(
383    .SIM_COLLISION_CHECK("NONE"),
384    .EN_ECC_READ("FALSE"),
385    .EN_ECC_WRITE("FALSE")
386 )
387 response_queue_inst (
388 .DI        (write_queue_data),
389     .DIP       (8'h0),
390 .RDADDR    (read_queue_addr),
391 .RDCLK     (log_clk),
392     .RDEN      (1'b1),
393     .REGCE     (1'b1),
394 .SSR       (log_rst),
395     .WE        ({8{expecting_a_response}}),
396 .WRADDR    (write_queue_addr),
397 .WRCLK     (log_clk),
398 .WREN      (expecting_a_response),
399 
400 .DO        (read_queue_data),
401 .DOP       (),
402 
403 .ECCPARITY (),
404 .SBITERR   (),
405 .DBITERR   ()
406 );
407 
408 
409   assign expected_tid   = read_queue_data_q[19:12];
410   assign expected_ftype = read_queue_data_q[11:8];
411   assign expected_size  = read_queue_data_q[7:0];
412   //}}} End of Response Queue ------------
413 
414 
415   //{{{ Response Side Check --------------
416 
417   //collect outgoing requests that require a response, queue them
418   always @(posedge log_clk) begin
419     if (log_rst_q) begin
420       expecting_a_response <= 1'b0;
421     end else if (current_beat_cnt == 0 && ireq_advance_condition) begin
422       expecting_a_response <= (current_ftype == NREAD) ||
423                               (current_ftype == DOORB) ||
424                               (current_ftype == MESSG) ||
425                               ((current_ftype == NWRITE) && (current_ttype ==TNWR_R));
426     end else begin
427       expecting_a_response <= 1'b0;
428     end
429   end
430   always @(posedge log_clk) begin
431     if (log_rst_q) begin
432       write_queue_addr <= 9'h000;
433     end else if (expecting_a_response) begin
434       write_queue_addr <= write_queue_addr + 1;
435     end
436   end
437 
438   always @(posedge log_clk) begin
439     if (log_rst_q) begin
440       read_queue_addr  <= 9'h000;
441       request_done     <= 1'b0;
442       compare_received <= 1'b1;
443     end else if (iresp_advance_condition && val_iresp_tlast && sent_all_packets &&
444                  (write_queue_addr == read_queue_addr + 1)) begin
445       request_done     <= 1'b1;
446       compare_received <= 1'b0;
447     end else if (sent_all_packets && (write_queue_addr == read_queue_addr)) begin
448       request_done     <= 1'b1;
449       compare_received <= 1'b0;
450     end else if (iresp_advance_condition && val_iresp_tlast && !request_autocheck_error) begin
451       read_queue_addr  <= read_queue_addr + 1;
452       compare_received <= 1'b1;
453     end else if (iresp_advance_condition) begin
454       compare_received <= 1'b0;
455     end
456   end
457 
458   always @ (posedge log_clk) begin
459     if (log_rst_q) begin
460       request_autocheck_error <= 1'b0;
461     end else if (compare_received && iresp_advance_condition) begin
462       if(expected_tid != val_iresp_tdata[63:56]) begin
463         //TID mismatch means an error unless it's a message response (MSGs don't use TID)
464         if (!(expected_ftype == MESSG) || !(val_iresp_tdata[51:48] == MSGRSP)) begin
465           request_autocheck_error <= 1'b1;
466           $display ("*** TID mismatch Error ***");
467         end
468       //expecting a Read response
469       end else if (expected_ftype == NREAD && !(val_iresp_tdata[51:48] == TWDATA)) begin
470         request_autocheck_error <= 1'b1;
471       $display ("*** NREAD Read Response Not Received ***");
472       //expecting a Response without data
473       end else if (expected_ftype == NWRITE && !(val_iresp_tdata[51:48] == TNDATA)) begin
474         request_autocheck_error <= 1'b1;
475       $display ("*** NWRITE Response Without Data Error ***");
476       //expecting a Response without data
477       end else if (expected_ftype == DOORB && !(val_iresp_tdata[51:48] == TNDATA)) begin
478         request_autocheck_error <= 1'b1;
479       $display ("*** DOORB Response Without Data Error ***");
480       end
481     end
482   end
483 
484   always @ (posedge log_clk) begin
485     if (log_rst_q) begin
486       val_iresp_tready    <= 1'b0;
487       delay_assert_tready <= 1'b0;
488 
489     end else if (iresp_advance_condition && val_iresp_tlast) begin
490       val_iresp_tready    <= 1'b0;
491       delay_assert_tready <= 1'b1;
492     end else if (delay_assert_tready) begin
493       val_iresp_tready    <= 1'b0;
494       delay_assert_tready <= 1'b0;
495     end else begin
496       val_iresp_tready    <= 1'b1;
497       delay_assert_tready <= 1'b0;
498     end
499   end
500 
501   //}}} End Response Side Check ----------
502 
503 
504 endmodule
505 //{{{ DISCLAIMER OF LIABILITY
506 //-----------------------------------------------------------------
507 //(c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
508 //
509 //This file contains confidential and proprietary information
510 //of Xilinx, Inc. and is protected under U.S. and
511 //international copyright and other intellectual property
512 //laws.
513 //
514 //DISCLAIMER
515 //This disclaimer is not a license and does not grant any
516 //rights to the materials distributed herewith. Except as
517 //otherwise provided in a valid license issued to you by
518 //Xilinx, and to the maximum extent permitted by applicable
519 //law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
520 //WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
521 //AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
522 //BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
523 //INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
524 //(2) Xilinx shall not be liable (whether in contract or tort,
525 //including negligence, or under any other theory of
526 //liability) for any loss or damage of any kind or nature
527 //related to, arising under or in connection with these
528 //materials, including for any direct, or any indirect,
529 //special, incidental, or consequential loss or damage
530 //(including loss of data, profits, goodwill, or any type of
531 //loss or damage suffered as a result of any action brought
532 //by a third party) even if such damage or loss was
533 //reasonably foreseeable or Xilinx had been advised of the
534 //possibility of the same.
535 //
536 //CRITICAL APPLICATIONS
537 //Xilinx products are not designed or intended to be fail-
538 //safe, or for use in any application requiring fail-safe
539 //performance, such as life-support or safety devices or
540 //systems, Class III medical devices, nuclear facilities,
541 //applications related to the deployment of airbags, or any
542 //other applications that could lead to death, personal
543 //injury, or severe property or environmental damage
544 //(individually and collectively, "Critical
545 //Applications"). Customer assumes the sole risk and
546 //liability of any use of Xilinx products in Critical
547 //Applications, subject only to applicable laws and
548 //regulations governing limitations on product liability.
549 //
550 //THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
551 //PART OF THIS FILE AT ALL TIMES.
552 //}}}

1 //
2 //(c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
3 //
4 //                                                                 
5 //This file contains confidential and proprietary information
6 //of Xilinx, Inc. and is protected under U.S. and
7 //international copyright and other intellectual property
8 //laws.
9 // 
10 //DISCLAIMER
11 //This disclaimer is not a license and does not grant any
12 //rights to the materials distributed herewith. Except as
13 //otherwise provided in a valid license issued to you by
14 //Xilinx, and to the maximum extent permitted by applicable
15 //law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16 //WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17 //AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18 //BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19 //INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20 //(2) Xilinx shall not be liable (whether in contract or tort,
21 //including negligence, or under any other theory of
22 //liability) for any loss or damage of any kind or nature
23 //related to, arising under or in connection with these
24 //materials, including for any direct, or any indirect,
25 //special, incidental, or consequential loss or damage
26 //(including loss of data, profits, goodwill, or any type of
27 //loss or damage suffered as a result of any action brought
28 //by a third party) even if such damage or loss was
29 //reasonably foreseeable or Xilinx had been advised of the
30 //possibility of the same.
31 // 
32 //CRITICAL APPLICATIONS
33 //Xilinx products are not designed or intended to be fail-
34 //safe, or for use in any application requiring fail-safe
35 //performance, such as life-support or safety devices or
36 //systems, Class III medical devices, nuclear facilities,
37 //applications related to the deployment of airbags, or any
38 //other applications that could lead to death, personal
39 //injury, or severe property or environmental damage
40 //(individually and collectively, "Critical
41 //Applications"). Customer assumes the sole risk and
42 //liability of any use of Xilinx products in Critical
43 //Applications, subject only to applicable laws and
44 //regulations governing limitations on product liability.
45 // 
46 //THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47 //PART OF THIS FILE AT ALL TIMES.                                
48 
49 `timescale 1ps/1ps
50 
51 modulesrio_response_gen_srio_gen2_0 (
52   inputlog_clk,
53   inputlog_rst,
54 
55   input      [15:0] deviceid,
56   input      [15:0] source_id,
57   inputid_override,
58 
59   output regval_tresp_tvalid,
60   inputval_tresp_tready,
61   output regval_tresp_tlast,
62   output reg [63:0] val_tresp_tdata,
63   output      [7:0] val_tresp_tkeep,
64   output     [31:0] val_tresp_tuser,
65 
66   inputval_treq_tvalid,
67   output regval_treq_tready,
68   inputval_treq_tlast,
69   input      [63:0] val_treq_tdata,
70   input       [7:0] val_treq_tkeep,
71   input      [31:0] val_treq_tuser
72 );
73 
74 
75   //{{{ local parameters -----------------
76 
77   localparam [3:0] NREAD  = 4'h2;
78   localparam [3:0] NWRITE = 4'h5;
79   localparam [3:0] SWRITE = 4'h6;
80   localparam [3:0] DOORB  = 4'hA;
81   localparam [3:0] MESSG  = 4'hB;
82   localparam [3:0] RESP   = 4'hD;
83 
84   localparam [3:0] TNWR   = 4'h4;
85   localparam [3:0] TNWR_R = 4'h5;
86   localparam [3:0] TNRD   = 4'h4;
87 
88   localparam [3:0] TNDATA = 4'h0;
89   localparam [3:0] MSGRSP = 4'h1;
90   localparam [3:0] TWDATA = 4'h8;
91 
92   //}}} End local parameters -------------
93 
94 
95   //{{{ wire declarations ----------------
96   reg  [15:0] log_rst_shift;
97   wire        log_rst_q = log_rst_shift[15];
98 
99   wire        treq_advance_condition  = val_treq_tready &&val_treq_tvalid;
100   wire        tresp_advance_condition = val_tresp_tready &&val_tresp_tvalid;
101 
102   //request side
103   wire [63:0] response_data_in_d;
104   reg  [63:0] response_data_in;
105   reg  [8:0]  response_wr_address;
106 
107   reggenerate_a_response;
108   regfirst_beat;
109 
110   //data storage
111   regcapture_data;
112   reg   [8:0] data_store_waddr;
113   reg   [8:0] data_store_raddr;
114   wiredata_store_wen;
115   wiredata_store_ren;
116   wire [63:0] data_store_dout;
117 
118   //incoming packet fields
119   wire  [7:0] current_tid;
120   wire  [3:0] current_ftype;
121   wire  [3:0] current_ttype;
122   wire  [7:0] current_size;
123   wire  [1:0] current_prio;
124   wire [33:0] current_addr;
125   wire [15:0] current_srcid;
126   wire [15:0] dest_id;
127   wire [15:0] src_id;
128   //outgoing packet fields
129   wire  [7:0] response_tid;
130   wire  [3:0] response_ftype;
131   wire  [3:0] response_ttype;
132   wire  [7:0] response_size;
133   wire  [1:0] response_prio;
134   wire [63:0] response_data_out_d;
135   reg  [46:0] response_data_out; //upper 63:47 unused
136   wire [8:0]  starting_read_addr;
137   wirepull_from_store;
138   regpull_from_store_q;
139   reg  [8:0]  response_rd_address;
140   regaddresses_differ;
141   regout_of_packet;
142   wirerd_increment;
143   regrd_increment_q, rd_increment_qq, rd_increment_qqq, rd_increment_qqqq;
144   regbefore_first_beat;
145   regfirst_packet_transfer;
146   regfirst_packet_transfer_q;
147 
148   wire  [3:0] responding_ttype;
149   wire [63:0] header_beat;
150   wire  [4:0] number_of_data_beats;
151   reg   [4:0] number_of_data_beats_q;
152   reg   [5:0] current_beat_cnt;
153   reg   [7:0] data_beat, data_beat_q;
154 
155   //}}} End wire declarations ------------
156 
157 
158   //{{{ Common-use Signals ---------------
159 
160   //Simple Assignments
161   assign val_tresp_tkeep  = 8'hFF;
162   assign src_id           = id_override ?source_id : deviceid;
163   assign val_tresp_tuser  ={src_id, dest_id};
164   //End Simple Assignments
165 
166   always @(posedge log_clk or posedge log_rst) begin
167     if(log_rst)
168       log_rst_shift <= 16'hFFFF;
169     else
170       log_rst_shift <= {log_rst_shift[14:0], 1'b0};
171   end
172 
173   always @(posedge log_clk) begin
174     if (log_rst_q) begin
175       number_of_data_beats_q   <= 5'h0;
176       rd_increment_q           <= 1'b0;
177       rd_increment_qq          <= 1'b0;
178       rd_increment_qqq         <= 1'b0;
179       rd_increment_qqqq        <= 1'b0;
180     end else begin
181       number_of_data_beats_q   <=number_of_data_beats;
182       rd_increment_q           <=rd_increment;
183       rd_increment_qq          <=rd_increment_q;
184       rd_increment_qqq         <=rd_increment_qq;
185       rd_increment_qqqq        <=rd_increment_qqq;
186     end
187   end
188   //}}} End Common-use Signals -----------
189 
190 
191   //{{{ Request Logic --------------------
192 
193   always @(posedge log_clk) begin
194     if (log_rst_q) begin
195       val_treq_tready     <= 1'b0;
196     //buffer full condition
197     end else if (((response_wr_address + 16'h1) == response_rd_address) ||
198                  ((response_wr_address + 16'h2) == response_rd_address)) begin
199       val_treq_tready     <= 1'b0;
200     end else begin
201       val_treq_tready     <= 1'b1;
202     end
203   end
204 
205   always @(posedge log_clk) begin
206     if (log_rst_q) begin
207       first_beat <= 1'b1;
208     end else if (treq_advance_condition && val_treq_tlast) begin
209       first_beat <= 1'b1;
210     end else if (treq_advance_condition) begin
211       first_beat <= 1'b0;
212     end
213   end
214   assign current_tid   = val_treq_tdata[63:56];
215   assign current_ftype = val_treq_tdata[55:52];
216   assign current_ttype = val_treq_tdata[51:48];
217   assign current_size  = val_treq_tdata[43:36];
218   assign current_prio  = val_treq_tdata[46:45] + 2'b01;
219   assign current_addr  = val_treq_tdata[33:0];
220   assign current_srcid = val_treq_tuser[31:16];
221 
222 
223   //collect incoming requests that require a response, queue them
224   always @(posedge log_clk) begin
225     if (log_rst_q) begin
226       generate_a_response <= 1'b0;
227     end else if (first_beat && treq_advance_condition) begin
228       generate_a_response <= (current_ftype == NREAD) ||
229                               (current_ftype == DOORB) ||
230                               (current_ftype == MESSG) ||
231                               ((current_ftype == NWRITE) && (current_ttype ==TNWR_R));
232     end else begin
233       generate_a_response <= 1'b0;
234     end
235   end
236   //}}} End Request Logic ----------------
237 
238 
239   //{{{ Local Data Storage ---------------
240   always @(posedge log_clk) begin
241     if (log_rst_q) begin
242       capture_data <= 1'b0;
243     end else if (first_beat && treq_advance_condition && current_addr[23:16] == 8'h12) begin
244       capture_data <= (current_ftype == SWRITE) || (current_ftype ==NWRITE);
245     end else if (treq_advance_condition && val_treq_tlast) begin
246       capture_data <= 1'b0;
247     end
248   end
249 
250   assign data_store_wen = capture_data &&treq_advance_condition;
251 
252   always @(posedge log_clk) begin
253     if (log_rst_q) begin
254       data_store_waddr <= 9'h0;
255     end else if (first_beat && treq_advance_condition) begin
256       data_store_waddr <= {1'b0, current_addr[10:3]};
257     end else if (treq_advance_condition) begin
258       data_store_waddr <= data_store_waddr + 1;
259     end
260   end
261 
262   always @(posedge log_clk) begin
263     if (log_rst_q) begin
264       data_store_raddr  <= 9'h0;
265       pull_from_store_q <= 1'b0;
266     end else if (pull_from_store && current_beat_cnt == 0 && !tresp_advance_condition &&
267                   (rd_increment_qqq || first_packet_transfer)) begin
268       data_store_raddr  <=starting_read_addr;
269       pull_from_store_q <= 1'b1;
270     end else if ((pull_from_store_q && tresp_advance_condition) || first_packet_transfer_q || rd_increment_qqqq) begin
271       data_store_raddr  <= data_store_raddr + 1;
272       pull_from_store_q <= !(val_tresp_tlast && !rd_increment_qqqq);
273     end
274   end
275 
276   assign data_store_ren = val_tresp_tready || !val_tresp_tvalid;
277 
278 RAMB36SDP #(
279    .SIM_COLLISION_CHECK("NONE"),
280    .EN_ECC_READ("FALSE"),
281    .EN_ECC_WRITE("FALSE")
282 )
283 local_data_store (
284 .DI        (val_treq_tdata),
285     .DIP       (8'h0),
286 .RDADDR    (data_store_raddr),
287 .RDCLK     (log_clk),
288 .RDEN      (data_store_ren),
289     .REGCE     (1'b1),
290 .SSR       (log_rst),
291     .WE        ({8{data_store_wen}}),
292 .WRADDR    (data_store_waddr),
293 .WRCLK     (log_clk),
294 .WREN      (data_store_wen),
295 
296 .DO        (data_store_dout),
297 .DOP       (),
298 
299 .ECCPARITY (),
300 .SBITERR   (),
301 .DBITERR   ()
302 );
303   //}}} End Local Data Storage -----------
304 
305 
306   //{{{ Request Queue --------------------
307   assign response_data_in_d = {17'h0, current_srcid, current_addr[23:16] == 8'h12, current_addr[10:3],
308 current_prio, current_tid, current_ftype, current_size};
309   always @ (posedge log_clk) begin
310     response_data_in <=response_data_in_d;
311   end
312 
313   always @(posedge log_clk) begin
314     if (log_rst_q) begin
315       out_of_packet <= 1'b0;
316     end else if (rd_increment) begin
317       out_of_packet <= 1'b0;
318     end else if (tresp_advance_condition && val_tresp_tlast) begin
319       out_of_packet <= 1'b1;
320     end
321   end
322   assign rd_increment  = ((tresp_advance_condition && val_tresp_tlast) || (out_of_packet)) &&
323                          (response_rd_address != response_wr_address) &&
324                          (response_rd_address + 1 !=response_wr_address);
325   always @(posedge log_clk) begin
326     if (log_rst_q) begin
327       response_wr_address <= 9'h0;
328       response_rd_address <= 9'h0;
329     end else begin
330       if(generate_a_response)
331         response_wr_address <= response_wr_address + 1;
332       if(rd_increment)
333         response_rd_address <= response_rd_address + 1;
334     end
335   end
336 
337 RAMB36SDP #(
338    .SIM_COLLISION_CHECK("NONE"),
339    .EN_ECC_READ("FALSE"),
340    .EN_ECC_WRITE("FALSE")
341 )
342 response_queue_inst (
343 .DI        (response_data_in),
344     .DIP       (8'h0),
345 .RDADDR    (response_rd_address),
346 .RDCLK     (log_clk),
347     .RDEN      (1'b1),
348     .REGCE     (1'b1),
349 .SSR       (log_rst),
350     .WE        ({8{generate_a_response}}),
351 .WRADDR    (response_wr_address),
352 .WRCLK     (log_clk),
353 .WREN      (generate_a_response),
354 
355 .DO        (response_data_out_d),
356 .DOP       (),
357 
358 .ECCPARITY (),
359 .SBITERR   (),
360 .DBITERR   ()
361 );
362 
363   always @ (posedge log_clk) begin
364     response_data_out  <= response_data_out_d[46:0];
365   end
366   assign response_tid   = response_data_out[19:12];
367   assign response_ftype = response_data_out[11:8];
368   assign response_size  = response_data_out[7:0];
369   assign response_prio  = response_data_out[21:20];
370   assign dest_id        = response_data_out[46:31];
371   assign starting_read_addr = {1'b0, response_data_out[29:22]};
372   assign pull_from_store = response_data_out[30];
373 
374   //}}} End of Request Queue -------------
375 
376 
377   //{{{ Response Logic -------------------
378   assign number_of_data_beats = current_beat_cnt == 0 ? response_size[7:3] : number_of_data_beats_q;
379 
380   always @(posedge log_clk) begin
381     if (log_rst_q) begin
382       current_beat_cnt <= 6'h0;
383     end else if (tresp_advance_condition && val_tresp_tlast) begin
384       current_beat_cnt <= 6'h0;
385     end else if (tresp_advance_condition) begin
386       current_beat_cnt <= current_beat_cnt + 1;
387     end
388   end
389 
390   always @(posedge log_clk) begin
391     if (log_rst_q) begin
392       val_tresp_tlast  <= 1'b0;
393     end else if (responding_ttype == TNDATA || responding_ttype == MSGRSP) begin
394       val_tresp_tlast  <= !(tresp_advance_condition &&val_tresp_tlast);
395     end else if (current_beat_cnt == {1'b0, number_of_data_beats} && tresp_advance_condition) begin
396       val_tresp_tlast  <= !val_tresp_tlast;
397     end else if (val_tresp_tready || !val_tresp_tvalid) begin
398       val_tresp_tlast  <= 1'b0;
399     end
400   end
401 
402   assign responding_ttype = (response_ftype == NREAD) ? TWDATA : (response_ftype == MESSG) ?MSGRSP : TNDATA;
403   assign header_beat = {response_tid, RESP, responding_ttype, 1'b0, response_prio, 45'h0};
404   always @(posedge log_clk) begin
405     if (current_beat_cnt == 0 && !tresp_advance_condition) begin
406       val_tresp_tdata  <=header_beat;
407     end else if (pull_from_store || pull_from_store_q) begin
408       if (tresp_advance_condition) begin
409         val_tresp_tdata  <=data_store_dout;
410       end
411     end else begin
412       val_tresp_tdata  <= {8{data_beat}};
413     end
414   end
415   always @* begin
416     data_beat =data_beat_q;
417     if (tresp_advance_condition && current_beat_cnt != 0) begin
418       data_beat = data_beat_q + 1;
419     end
420   end
421   always @(posedge log_clk) begin
422     if (log_rst_q) begin
423       data_beat_q <= 8'h00;
424     end else begin
425       data_beat_q <=data_beat;
426     end
427   end
428 
429   always @(posedge log_clk) begin
430     if (log_rst_q) begin
431       before_first_beat     <= 1'b1;
432     end else if (addresses_differ) begin
433       before_first_beat     <= 1'b0;
434     end
435   end
436   always @(posedge log_clk) begin
437     if (log_rst_q) begin
438       addresses_differ     <= 1'b0;
439     end else if (response_rd_address != response_wr_address) begin
440       addresses_differ      <= 1'b1;
441     end
442   end
443   always @(posedge log_clk) begin
444     if (log_rst_q) begin
445       first_packet_transfer <= 1'b0;
446     end else if (before_first_beat && addresses_differ) begin
447       first_packet_transfer <= 1'b1;
448     end else begin
449       first_packet_transfer <= 1'b0;
450     end
451   end
452   always @(posedge log_clk) begin
453     if (log_rst_q) begin
454       first_packet_transfer_q <= 1'b0;
455     end else begin
456       first_packet_transfer_q <=first_packet_transfer;
457     end
458   end
459   always @(posedge log_clk) begin
460     if (log_rst_q) begin
461       val_tresp_tvalid <= 1'b0;
462     end else if (first_packet_transfer_q) begin
463       val_tresp_tvalid <= 1'b1;
464     end else if (rd_increment_qqqq) begin
465       val_tresp_tvalid <= 1'b1;
466     end else if (tresp_advance_condition && val_tresp_tlast) begin
467       val_tresp_tvalid <= 1'b0;
468     end
469   end
470 
471   //}}} End Response Logic ---------------
472 
473 
474 endmodule
475 //{{{ DISCLAIMER OF LIABILITY
476 //-----------------------------------------------------------------
477 //(c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
478 //
479 //This file contains confidential and proprietary information
480 //of Xilinx, Inc. and is protected under U.S. and
481 //international copyright and other intellectual property
482 //laws.
483 //
484 //DISCLAIMER
485 //This disclaimer is not a license and does not grant any
486 //rights to the materials distributed herewith. Except as
487 //otherwise provided in a valid license issued to you by
488 //Xilinx, and to the maximum extent permitted by applicable
489 //law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
490 //WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
491 //AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
492 //BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
493 //INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
494 //(2) Xilinx shall not be liable (whether in contract or tort,
495 //including negligence, or under any other theory of
496 //liability) for any loss or damage of any kind or nature
497 //related to, arising under or in connection with these
498 //materials, including for any direct, or any indirect,
499 //special, incidental, or consequential loss or damage
500 //(including loss of data, profits, goodwill, or any type of
501 //loss or damage suffered as a result of any action brought
502 //by a third party) even if such damage or loss was
503 //reasonably foreseeable or Xilinx had been advised of the
504 //possibility of the same.
505 //
506 //CRITICAL APPLICATIONS
507 //Xilinx products are not designed or intended to be fail-
508 //safe, or for use in any application requiring fail-safe
509 //performance, such as life-support or safety devices or
510 //systems, Class III medical devices, nuclear facilities,
511 //applications related to the deployment of airbags, or any
512 //other applications that could lead to death, personal
513 //injury, or severe property or environmental damage
514 //(individually and collectively, "Critical
515 //Applications"). Customer assumes the sole risk and
516 //liability of any use of Xilinx products in Critical
517 //Applications, subject only to applicable laws and
518 //regulations governing limitations on product liability.
519 //
520 //THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
521 //PART OF THIS FILE AT ALL TIMES.
522 //}}}

1 //
2 //(c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
3 //
4 //                                                                 
5 //This file contains confidential and proprietary information
6 //of Xilinx, Inc. and is protected under U.S. and
7 //international copyright and other intellectual property
8 //laws.
9 // 
10 //DISCLAIMER
11 //This disclaimer is not a license and does not grant any
12 //rights to the materials distributed herewith. Except as
13 //otherwise provided in a valid license issued to you by
14 //Xilinx, and to the maximum extent permitted by applicable
15 //law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16 //WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17 //AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18 //BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19 //INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20 //(2) Xilinx shall not be liable (whether in contract or tort,
21 //including negligence, or under any other theory of
22 //liability) for any loss or damage of any kind or nature
23 //related to, arising under or in connection with these
24 //materials, including for any direct, or any indirect,
25 //special, incidental, or consequential loss or damage
26 //(including loss of data, profits, goodwill, or any type of
27 //loss or damage suffered as a result of any action brought
28 //by a third party) even if such damage or loss was
29 //reasonably foreseeable or Xilinx had been advised of the
30 //possibility of the same.
31 // 
32 //CRITICAL APPLICATIONS
33 //Xilinx products are not designed or intended to be fail-
34 //safe, or for use in any application requiring fail-safe
35 //performance, such as life-support or safety devices or
36 //systems, Class III medical devices, nuclear facilities,
37 //applications related to the deployment of airbags, or any
38 //other applications that could lead to death, personal
39 //injury, or severe property or environmental damage
40 //(individually and collectively, "Critical
41 //Applications"). Customer assumes the sole risk and
42 //liability of any use of Xilinx products in Critical
43 //Applications, subject only to applicable laws and
44 //regulations governing limitations on product liability.
45 // 
46 //THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47 //PART OF THIS FILE AT ALL TIMES.                                
48 //----------------------------------------------------------------------
49 //
50 //SRIO_QUICK_START
51 //Description:
52 //This module sends a fixed set of instructions to the configuration
53 //register space, both local and remote.
54 //
55 //Hierarchy:
56 //SRIO_EXAMPLE_TOP
57 //|____> SRIO_DUT
58 //|____> SRIO_STATISTICS
59 //|____> SRIO_REPORT
60 //|____> SRIO_REQUEST_GEN
61 //|____> SRIO_RESPONSE_GEN
62 //|____> SRIO_QUICK_START
63 //
64 //---------------------------------------------------------------------
65 
66 `timescale 1ps/1ps
67 
68 modulesrio_quick_start_srio_gen2_0 (
69   inputlog_clk,
70   inputlog_rst,
71 
72   output regmaintr_awvalid,
73   inputmaintr_awready,
74   output     [31:0] maintr_awaddr,
75 
76   output regmaintr_wvalid,
77   inputmaintr_wready,
78   output     [31:0] maintr_wdata,
79   inputmaintr_bvalid,
80   outputmaintr_bready,
81   input       [1:0] maintr_bresp,
82 
83   output regmaintr_arvalid,
84   inputmaintr_arready,
85   output     [31:0] maintr_araddr,
86 
87   inputmaintr_rvalid,
88   outputmaintr_rready,
89   input      [31:0] maintr_rdata,
90   input       [1:0] maintr_rresp,
91 
92   inputgo,
93   input       [3:0] user_hop,
94   inputuser_inst,
95   input      [23:0] user_addr,
96   input      [31:0] user_data,
97 
98   inputlink_initialized,
99   output regmaint_done,
100   output regmaint_autocheck_error
101 );
102 
103 
104   //{{{ local parameters -----------------
105   localparam [8:0] STARTING_ADDRESS       = 9'h0;
106   localparam       NUMBER_OF_INSTRUCTIONS = 20;
107 
108   localparam       READ      = 1'b1;
109   localparam       WRITE     = 1'b0;
110   localparam       LOCAL     = 1'b0;
111   localparam       REMTE     = 1'b1;
112 
113   localparam [3:0] MAINT     = 4'h8;
114 
115   localparam [3:0] RDREQ     = 4'h0;
116   localparam [3:0] WRREQ     = 4'h1;
117 
118   localparam [7:0] HOP_LOCAL = 8'h00;
119   localparam [7:0] HOP_REMTE = 8'hFF;
120 
121 
122   `include "maintenance_list.vh"
123   //}}} End local parameters -------------
124 
125 
126   //{{{ wire declarations ----------------
127   reg  [15:0] log_rst_shift;
128   wire        log_rst_q = log_rst_shift[15];
129 
130   reg  [10:0] link_initialized_cnt;
131   wire        link_initialized_delay = link_initialized_cnt[10];
132 
133   wire [63:0] maint_data_out_d;
134   reg  [61:0] maint_data_out; //upper 63:62 bits unused
135   reg   [8:0] maint_address;
136   reggo_q;
137   wirego_rose;
138 
139   wire        maint_req_advance_condition  = (maintr_awready && maintr_awvalid) ||
140                                              (maintr_arready &&maintr_arvalid);
141   wire        maint_bresp_advance_condition  = (maintr_bready &&maintr_bvalid);
142   wire        maint_resp_advance_condition   = (maintr_rready &&maintr_rvalid);
143 
144   reglast_packet_beat_q, last_packet_beat_qq, last_packet_beat_qqq;
145   reg  [15:0] instruction_cnt;
146   wire [32:0] data_mask = { {8{maint_data_out[3]}}, {8{maint_data_out[2]}},
147                             {8{maint_data_out[1]}}, {8{maint_data_out[0]}} };
148   //}}} End wire declarations ------------
149 
150 
151   //{{{ Common-use Signals ---------------
152 
153 
154   always @(posedge log_clk or posedge log_rst) begin
155     if(log_rst)
156       log_rst_shift <= 16'hFFFF;
157     else
158       log_rst_shift <= {log_rst_shift[14:0], 1'b0};
159   end
160 
161   always @(posedge log_clk) begin
162     if (log_rst_q) begin
163       last_packet_beat_q       <= 1'b1;
164       last_packet_beat_qq      <= 1'b1;
165       last_packet_beat_qqq     <= 1'b1;
166       go_q                     <= 1'b0;
167     end else begin
168       last_packet_beat_q       <= maint_resp_advance_condition ||maint_bresp_advance_condition;
169       last_packet_beat_qq      <=last_packet_beat_q;
170       last_packet_beat_qqq     <= last_packet_beat_qq || !link_initialized_delay;
171       go_q                     <=go;
172     end
173   end
174 
175   //put a sufficient delay on the initialization to improve simulation time.
176   //Not needed for actual hardware but does no damage if kept.
177   always @(posedge log_clk) begin
178     if (log_rst_q) begin
179       link_initialized_cnt <= 0;
180     end else if (link_initialized && !link_initialized_delay) begin
181       link_initialized_cnt <= link_initialized_cnt + 1;
182     end else if (!link_initialized) begin
183       link_initialized_cnt <= 0;
184     end
185   end
186 
187   assign go_rose = go && !go_q;
188   //}}} End Common-use Signals -----------
189 
190 
191   //{{{ Request Packet Formatter ---------
192   always @(posedge log_clk) begin
193     if (log_rst_q) begin
194       maint_address <=STARTING_ADDRESS;
195     end else if (maint_resp_advance_condition || maint_bresp_advance_condition) begin
196       maint_address <= maint_address + 1;
197     end
198   end
199 
200   assign maintr_wdata = go ? user_data : maint_data_out[35:4];
201 
202   assign maintr_bready = 1'b1;
203   assign maintr_rready = 1'b1;
204 
205   assign maintr_araddr = go ? { 4'h0, user_hop, user_addr} : maint_data_out[61:37];
206   assign maintr_awaddr = go ? { 4'h0, user_hop, user_addr} : maint_data_out[61:37];
207 
208   always @(posedge log_clk) begin
209     if (log_rst_q) begin
210       maintr_awvalid   <= 1'b0;
211       maintr_wvalid    <= 1'b0;
212       maintr_arvalid   <= 1'b0;
213       instruction_cnt  <= 16'h0;
214     end else if (link_initialized_delay &&
215                  (instruction_cnt < NUMBER_OF_INSTRUCTIONS && last_packet_beat_qqq) || go_rose) begin
216       maintr_awvalid   <= go ? user_inst == WRITE : maint_data_out[36] ==WRITE;
217       maintr_wvalid    <= go ? user_inst == WRITE : maint_data_out[36] ==WRITE;
218       maintr_arvalid   <= go ? user_inst == READ  : maint_data_out[36] ==READ;
219     end else if (maint_req_advance_condition) begin
220       maintr_awvalid   <= 1'b0;
221       maintr_wvalid    <= 1'b0;
222       maintr_arvalid   <= 1'b0;
223       instruction_cnt  <= instruction_cnt + 1;
224     end else if (instruction_cnt == NUMBER_OF_INSTRUCTIONS) begin
225       maintr_awvalid   <= 1'b0;
226       maintr_wvalid    <= 1'b0;
227       maintr_arvalid   <= 1'b0;
228     end
229   end
230   //}}} End Request Packet Formatter -----
231 
232   //{{{ Request generation ---------------
233 RAMB36SDP #(
234    .SIM_COLLISION_CHECK("NONE"),
235    .EN_ECC_READ("FALSE"),
236    .EN_ECC_WRITE("FALSE"),
237 
238 .INIT_00({MAINTENANCE3  , MAINTENANCE2  , MAINTENANCE1  , MAINTENANCE0}  ),
239 .INIT_01({MAINTENANCE7  , MAINTENANCE6  , MAINTENANCE5  , MAINTENANCE4}  ),
240 .INIT_02({MAINTENANCE11 , MAINTENANCE10 , MAINTENANCE9  , MAINTENANCE8}  ),
241 .INIT_03({MAINTENANCE15 , MAINTENANCE14 , MAINTENANCE13 , MAINTENANCE12} ),
242 .INIT_04({MAINTENANCE19 , MAINTENANCE18 , MAINTENANCE17 , MAINTENANCE16} ),
243 .INIT_05({MAINTENANCE23 , MAINTENANCE22 , MAINTENANCE21 , MAINTENANCE20} ),
244 .INIT_06({MAINTENANCE27 , MAINTENANCE26 , MAINTENANCE25 , MAINTENANCE24} ),
245 .INIT_07({MAINTENANCE31 , MAINTENANCE30 , MAINTENANCE29 , MAINTENANCE28} ),
246 .INIT_08({MAINTENANCE35 , MAINTENANCE34 , MAINTENANCE33 , MAINTENANCE32} ),
247 .INIT_09({MAINTENANCE39 , MAINTENANCE38 , MAINTENANCE37 , MAINTENANCE36} ),
248 .INIT_0A({MAINTENANCE43 , MAINTENANCE42 , MAINTENANCE41 , MAINTENANCE40} ),
249 .INIT_0B({MAINTENANCE47 , MAINTENANCE46 , MAINTENANCE45 , MAINTENANCE44} ),
250 .INIT_0C({MAINTENANCE51 , MAINTENANCE50 , MAINTENANCE49 , MAINTENANCE48} ),
251 .INIT_0D({MAINTENANCE55 , MAINTENANCE54 , MAINTENANCE53 , MAINTENANCE52} ),
252 .INIT_0E({MAINTENANCE59 , MAINTENANCE58 , MAINTENANCE57 , MAINTENANCE56} ),
253 .INIT_0F({MAINTENANCE63 , MAINTENANCE62 , MAINTENANCE61 , MAINTENANCE60} ),
254 .INIT_10({MAINTENANCE67 , MAINTENANCE66 , MAINTENANCE65 , MAINTENANCE64} ),
255 .INIT_11({MAINTENANCE71 , MAINTENANCE70 , MAINTENANCE69 , MAINTENANCE68} ),
256 .INIT_12({MAINTENANCE75 , MAINTENANCE74 , MAINTENANCE73 , MAINTENANCE72} ),
257 .INIT_13({MAINTENANCE79 , MAINTENANCE78 , MAINTENANCE77 , MAINTENANCE76} ),
258 .INIT_14({MAINTENANCE83 , MAINTENANCE82 , MAINTENANCE81 , MAINTENANCE80} ),
259 .INIT_15({MAINTENANCE87 , MAINTENANCE86 , MAINTENANCE85 , MAINTENANCE84} ),
260 .INIT_16({MAINTENANCE91 , MAINTENANCE90 , MAINTENANCE89 , MAINTENANCE88} ),
261 .INIT_17({MAINTENANCE95 , MAINTENANCE94 , MAINTENANCE93 , MAINTENANCE92} ),
262 .INIT_18({MAINTENANCE99 , MAINTENANCE98 , MAINTENANCE97 , MAINTENANCE96} ),
263 .INIT_19({MAINTENANCE103, MAINTENANCE102, MAINTENANCE101, MAINTENANCE100}),
264 .INIT_1A({MAINTENANCE107, MAINTENANCE106, MAINTENANCE105, MAINTENANCE104}),
265 .INIT_1B({MAINTENANCE111, MAINTENANCE110, MAINTENANCE109, MAINTENANCE108}),
266 .INIT_1C({MAINTENANCE115, MAINTENANCE114, MAINTENANCE113, MAINTENANCE112}),
267 .INIT_1D({MAINTENANCE119, MAINTENANCE118, MAINTENANCE117, MAINTENANCE116}),
268 .INIT_1E({MAINTENANCE123, MAINTENANCE122, MAINTENANCE121, MAINTENANCE120}),
269 .INIT_1F({MAINTENANCE127, MAINTENANCE126, MAINTENANCE125, MAINTENANCE124}),
270 .INIT_20({MAINTENANCE131, MAINTENANCE130, MAINTENANCE129, MAINTENANCE128}),
271 .INIT_21({MAINTENANCE135, MAINTENANCE134, MAINTENANCE133, MAINTENANCE132}),
272 .INIT_22({MAINTENANCE139, MAINTENANCE138, MAINTENANCE137, MAINTENANCE136}),
273 .INIT_23({MAINTENANCE143, MAINTENANCE142, MAINTENANCE141, MAINTENANCE140}),
274 .INIT_24({MAINTENANCE147, MAINTENANCE146, MAINTENANCE145, MAINTENANCE144}),
275 .INIT_25({MAINTENANCE151, MAINTENANCE150, MAINTENANCE149, MAINTENANCE148}),
276 .INIT_26({MAINTENANCE155, MAINTENANCE154, MAINTENANCE153, MAINTENANCE152}),
277 .INIT_27({MAINTENANCE159, MAINTENANCE158, MAINTENANCE157, MAINTENANCE156}),
278 .INIT_28({MAINTENANCE163, MAINTENANCE162, MAINTENANCE161, MAINTENANCE160}),
279 .INIT_29({MAINTENANCE167, MAINTENANCE166, MAINTENANCE165, MAINTENANCE164}),
280 .INIT_2A({MAINTENANCE171, MAINTENANCE170, MAINTENANCE169, MAINTENANCE168}),
281 .INIT_2B({MAINTENANCE175, MAINTENANCE174, MAINTENANCE173, MAINTENANCE172}),
282 .INIT_2C({MAINTENANCE179, MAINTENANCE178, MAINTENANCE177, MAINTENANCE176}),
283 .INIT_2D({MAINTENANCE183, MAINTENANCE182, MAINTENANCE181, MAINTENANCE180}),
284 .INIT_2E({MAINTENANCE187, MAINTENANCE186, MAINTENANCE185, MAINTENANCE184}),
285 .INIT_2F({MAINTENANCE191, MAINTENANCE190, MAINTENANCE189, MAINTENANCE188}),
286 .INIT_30({MAINTENANCE195, MAINTENANCE194, MAINTENANCE193, MAINTENANCE192}),
287 .INIT_31({MAINTENANCE199, MAINTENANCE198, MAINTENANCE197, MAINTENANCE196}),
288 .INIT_32({MAINTENANCE203, MAINTENANCE202, MAINTENANCE201, MAINTENANCE200}),
289 .INIT_33({MAINTENANCE207, MAINTENANCE206, MAINTENANCE205, MAINTENANCE204}),
290 .INIT_34({MAINTENANCE211, MAINTENANCE210, MAINTENANCE209, MAINTENANCE208}),
291 .INIT_35({MAINTENANCE215, MAINTENANCE214, MAINTENANCE213, MAINTENANCE212}),
292 .INIT_36({MAINTENANCE219, MAINTENANCE218, MAINTENANCE217, MAINTENANCE216}),
293 .INIT_37({MAINTENANCE223, MAINTENANCE222, MAINTENANCE221, MAINTENANCE220}),
294 .INIT_38({MAINTENANCE227, MAINTENANCE226, MAINTENANCE225, MAINTENANCE224}),
295 .INIT_39({MAINTENANCE231, MAINTENANCE230, MAINTENANCE229, MAINTENANCE228}),
296 .INIT_3A({MAINTENANCE235, MAINTENANCE234, MAINTENANCE233, MAINTENANCE232}),
297 .INIT_3B({MAINTENANCE239, MAINTENANCE238, MAINTENANCE237, MAINTENANCE236}),
298 .INIT_3C({MAINTENANCE243, MAINTENANCE242, MAINTENANCE241, MAINTENANCE240}),
299 .INIT_3D({MAINTENANCE247, MAINTENANCE246, MAINTENANCE245, MAINTENANCE244}),
300 .INIT_3E({MAINTENANCE251, MAINTENANCE250, MAINTENANCE249, MAINTENANCE248}),
301 .INIT_3F({MAINTENANCE255, MAINTENANCE254, MAINTENANCE253, MAINTENANCE252}),
302 .INIT_40({MAINTENANCE259, MAINTENANCE258, MAINTENANCE257, MAINTENANCE256}),
303 .INIT_41({MAINTENANCE263, MAINTENANCE262, MAINTENANCE261, MAINTENANCE260}),
304 .INIT_42({MAINTENANCE267, MAINTENANCE266, MAINTENANCE265, MAINTENANCE264}),
305 .INIT_43({MAINTENANCE271, MAINTENANCE270, MAINTENANCE269, MAINTENANCE268}),
306 .INIT_44({MAINTENANCE275, MAINTENANCE274, MAINTENANCE273, MAINTENANCE272}),
307 .INIT_45({MAINTENANCE279, MAINTENANCE278, MAINTENANCE277, MAINTENANCE276}),
308 .INIT_46({MAINTENANCE283, MAINTENANCE282, MAINTENANCE281, MAINTENANCE280}),
309 .INIT_47({MAINTENANCE287, MAINTENANCE286, MAINTENANCE285, MAINTENANCE284}),
310 .INIT_48({MAINTENANCE291, MAINTENANCE290, MAINTENANCE289, MAINTENANCE288}),
311 .INIT_49({MAINTENANCE295, MAINTENANCE294, MAINTENANCE293, MAINTENANCE292}),
312 .INIT_4A({MAINTENANCE299, MAINTENANCE298, MAINTENANCE297, MAINTENANCE296}),
313 .INIT_4B({MAINTENANCE303, MAINTENANCE302, MAINTENANCE301, MAINTENANCE300}),
314 .INIT_4C({MAINTENANCE307, MAINTENANCE306, MAINTENANCE305, MAINTENANCE304}),
315 .INIT_4D({MAINTENANCE311, MAINTENANCE310, MAINTENANCE309, MAINTENANCE308}),
316 .INIT_4E({MAINTENANCE315, MAINTENANCE314, MAINTENANCE313, MAINTENANCE312}),
317 .INIT_4F({MAINTENANCE319, MAINTENANCE318, MAINTENANCE317, MAINTENANCE316}),
318 .INIT_50({MAINTENANCE323, MAINTENANCE322, MAINTENANCE321, MAINTENANCE320}),
319 .INIT_51({MAINTENANCE327, MAINTENANCE326, MAINTENANCE325, MAINTENANCE324}),
320 .INIT_52({MAINTENANCE331, MAINTENANCE330, MAINTENANCE329, MAINTENANCE328}),
321 .INIT_53({MAINTENANCE335, MAINTENANCE334, MAINTENANCE333, MAINTENANCE332}),
322 .INIT_54({MAINTENANCE339, MAINTENANCE338, MAINTENANCE337, MAINTENANCE336}),
323 .INIT_55({MAINTENANCE343, MAINTENANCE342, MAINTENANCE341, MAINTENANCE340}),
324 .INIT_56({MAINTENANCE347, MAINTENANCE346, MAINTENANCE345, MAINTENANCE344}),
325 .INIT_57({MAINTENANCE351, MAINTENANCE350, MAINTENANCE349, MAINTENANCE348}),
326 .INIT_58({MAINTENANCE355, MAINTENANCE354, MAINTENANCE353, MAINTENANCE352}),
327 .INIT_59({MAINTENANCE359, MAINTENANCE358, MAINTENANCE357, MAINTENANCE356}),
328 .INIT_5A({MAINTENANCE363, MAINTENANCE362, MAINTENANCE361, MAINTENANCE360}),
329 .INIT_5B({MAINTENANCE367, MAINTENANCE366, MAINTENANCE365, MAINTENANCE364}),
330 .INIT_5C({MAINTENANCE371, MAINTENANCE370, MAINTENANCE369, MAINTENANCE368}),
331 .INIT_5D({MAINTENANCE375, MAINTENANCE374, MAINTENANCE373, MAINTENANCE372}),
332 .INIT_5E({MAINTENANCE379, MAINTENANCE378, MAINTENANCE377, MAINTENANCE376}),
333 .INIT_5F({MAINTENANCE383, MAINTENANCE382, MAINTENANCE381, MAINTENANCE380}),
334 .INIT_60({MAINTENANCE387, MAINTENANCE386, MAINTENANCE385, MAINTENANCE384}),
335 .INIT_61({MAINTENANCE391, MAINTENANCE390, MAINTENANCE389, MAINTENANCE388}),
336 .INIT_62({MAINTENANCE395, MAINTENANCE394, MAINTENANCE393, MAINTENANCE392}),
337 .INIT_63({MAINTENANCE399, MAINTENANCE398, MAINTENANCE397, MAINTENANCE396}),
338 .INIT_64({MAINTENANCE403, MAINTENANCE402, MAINTENANCE401, MAINTENANCE400}),
339 .INIT_65({MAINTENANCE407, MAINTENANCE406, MAINTENANCE405, MAINTENANCE404}),
340 .INIT_66({MAINTENANCE411, MAINTENANCE410, MAINTENANCE409, MAINTENANCE408}),
341 .INIT_67({MAINTENANCE415, MAINTENANCE414, MAINTENANCE413, MAINTENANCE412}),
342 .INIT_68({MAINTENANCE419, MAINTENANCE418, MAINTENANCE417, MAINTENANCE416}),
343 .INIT_69({MAINTENANCE423, MAINTENANCE422, MAINTENANCE421, MAINTENANCE420}),
344 .INIT_6A({MAINTENANCE427, MAINTENANCE426, MAINTENANCE425, MAINTENANCE424}),
345 .INIT_6B({MAINTENANCE431, MAINTENANCE430, MAINTENANCE429, MAINTENANCE428}),
346 .INIT_6C({MAINTENANCE435, MAINTENANCE434, MAINTENANCE433, MAINTENANCE432}),
347 .INIT_6D({MAINTENANCE439, MAINTENANCE438, MAINTENANCE437, MAINTENANCE436}),
348 .INIT_6E({MAINTENANCE443, MAINTENANCE442, MAINTENANCE441, MAINTENANCE440}),
349 .INIT_6F({MAINTENANCE447, MAINTENANCE446, MAINTENANCE445, MAINTENANCE444}),
350 .INIT_70({MAINTENANCE451, MAINTENANCE450, MAINTENANCE449, MAINTENANCE448}),
351 .INIT_71({MAINTENANCE455, MAINTENANCE454, MAINTENANCE453, MAINTENANCE452}),
352 .INIT_72({MAINTENANCE459, MAINTENANCE458, MAINTENANCE457, MAINTENANCE456}),
353 .INIT_73({MAINTENANCE463, MAINTENANCE462, MAINTENANCE461, MAINTENANCE460}),
354 .INIT_74({MAINTENANCE467, MAINTENANCE466, MAINTENANCE465, MAINTENANCE464}),
355 .INIT_75({MAINTENANCE471, MAINTENANCE470, MAINTENANCE469, MAINTENANCE468}),
356 .INIT_76({MAINTENANCE475, MAINTENANCE474, MAINTENANCE473, MAINTENANCE472}),
357 .INIT_77({MAINTENANCE479, MAINTENANCE478, MAINTENANCE477, MAINTENANCE476}),
358 .INIT_78({MAINTENANCE483, MAINTENANCE482, MAINTENANCE481, MAINTENANCE480}),
359 .INIT_79({MAINTENANCE487, MAINTENANCE486, MAINTENANCE485, MAINTENANCE484}),
360 .INIT_7A({MAINTENANCE491, MAINTENANCE490, MAINTENANCE489, MAINTENANCE488}),
361 .INIT_7B({MAINTENANCE495, MAINTENANCE494, MAINTENANCE493, MAINTENANCE492}),
362 .INIT_7C({MAINTENANCE499, MAINTENANCE498, MAINTENANCE497, MAINTENANCE496}),
363 .INIT_7D({MAINTENANCE503, MAINTENANCE502, MAINTENANCE501, MAINTENANCE500}),
364 .INIT_7E({MAINTENANCE507, MAINTENANCE506, MAINTENANCE505, MAINTENANCE504}),
365 .INIT_7F({MAINTENANCE511, MAINTENANCE510, MAINTENANCE509, MAINTENANCE508})
366 )
367 maintenance_data_inst (
368     .DI        (64'h0),
369     .DIP       (8'h0),
370 .RDADDR    (maint_address),
371 .RDCLK     (log_clk),
372     .RDEN      (1'b1),
373     .REGCE     (1'b1),
374 .SSR       (log_rst),
375     .WE        (8'h0),
376     .WRADDR    (9'h0),
377 .WRCLK     (log_clk),
378     .WREN      (1'b0),
379 
380 .DO        (maint_data_out_d),
381 .DOP       (),
382 
383 .ECCPARITY (),
384 .SBITERR   (),
385 .DBITERR   ()
386 );
387   always @ (posedge log_clk) begin
388     maint_data_out  <= maint_data_out_d[61:0];
389   end
390 
391 
392   //}}} End of Request Generation --------
393 
394 
395   //{{{ Response Side Check --------------
396 
397   always @ (posedge log_clk) begin
398     if (log_rst_q) begin
399       maint_autocheck_error <= 1'b0;
400     end else if (maint_resp_advance_condition && maint_data_out[36] == READ) begin
401       if ((maintr_wdata & data_mask) != (maintr_rdata & data_mask)) begin
402         maint_autocheck_error <= 1'b1;
403       end else begin
404         maint_autocheck_error <= 1'b0;
405       end
406     end
407   end
408 
409   always @ (posedge log_clk) begin
410     if (log_rst_q) begin
411       maint_done <= 1'b0;
412     end else if ((instruction_cnt == NUMBER_OF_INSTRUCTIONS) &&
413                  (maint_bresp_advance_condition || maint_resp_advance_condition)) begin
414       maint_done <= 1'b1;
415     end
416   end
417 
418   //}}} End Response Side Check ----------
419 
420 
421 endmodule
422 //{{{ DISCLAIMER OF LIABILITY
423 //-----------------------------------------------------------------
424 //(c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
425 //
426 //This file contains confidential and proprietary information
427 //of Xilinx, Inc. and is protected under U.S. and
428 //international copyright and other intellectual property
429 //laws.
430 //
431 //DISCLAIMER
432 //This disclaimer is not a license and does not grant any
433 //rights to the materials distributed herewith. Except as
434 //otherwise provided in a valid license issued to you by
435 //Xilinx, and to the maximum extent permitted by applicable
436 //law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
437 //WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
438 //AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
439 //BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
440 //INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
441 //(2) Xilinx shall not be liable (whether in contract or tort,
442 //including negligence, or under any other theory of
443 //liability) for any loss or damage of any kind or nature
444 //related to, arising under or in connection with these
445 //materials, including for any direct, or any indirect,
446 //special, incidental, or consequential loss or damage
447 //(including loss of data, profits, goodwill, or any type of
448 //loss or damage suffered as a result of any action brought
449 //by a third party) even if such damage or loss was
450 //reasonably foreseeable or Xilinx had been advised of the
451 //possibility of the same.
452 //
453 //CRITICAL APPLICATIONS
454 //Xilinx products are not designed or intended to be fail-
455 //safe, or for use in any application requiring fail-safe
456 //performance, such as life-support or safety devices or
457 //systems, Class III medical devices, nuclear facilities,
458 //applications related to the deployment of airbags, or any
459 //other applications that could lead to death, personal
460 //injury, or severe property or environmental damage
461 //(individually and collectively, "Critical
462 //Applications"). Customer assumes the sole risk and
463 //liability of any use of Xilinx products in Critical
464 //Applications, subject only to applicable laws and
465 //regulations governing limitations on product liability.
466 //
467 //THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
468 //PART OF THIS FILE AT ALL TIMES.
469 //}}}